From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Mar 2013 18:06:28 +0000 (+0100)
Subject: Tiny bugfix in simlib.v
X-Git-Tag: yosys-0.2.0~679
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=26f2439551697c0511bd0c5375ce69e26973d4ca;p=yosys.git

Tiny bugfix in simlib.v
---

diff --git a/techlibs/simlib.v b/techlibs/simlib.v
index 29c13503b..8675a4d0f 100644
--- a/techlibs/simlib.v
+++ b/techlibs/simlib.v
@@ -646,7 +646,6 @@ module \$sr (S, R, Q);
 
 parameter WIDTH = 0;
 
-input CLK;
 input [WIDTH-1:0] S, R;
 output reg [WIDTH-1:0] Q;