From: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
Date: Thu, 14 Feb 2019 08:23:17 +0000 (+0100)
Subject: Turned the add_0 verilog state into nmigen
X-Git-Tag: ls180-24jan2020~2025
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27144dd663214de35c5f97f8cca3396401d470d0;p=ieee754fpu.git

Turned the add_0 verilog state into nmigen
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 1b9af670..119b1356 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -183,6 +183,22 @@ class FPADD:
                         m.d.sync += b_e.eq(-126) # limit b exponent
                     with m.Else():
                         m.d.sync += b_m[26].eq(1) # set highest mantissa bit
+
+            with m.State("add_0"):
+              m.next = "add_1"
+              m.d.sync += z_e.eq(a_e)
+              with m.If(a_s == b_s):
+                m.d.sync += [
+                tot.eq(a_m + b_m),
+                z_s.eq(a_s)]
+              with m.Else(a_m >= b_m):
+                m.d.sync += [
+                tot.eq(a_m - b_m),
+                z_s.eq(a_s)]
+              with m.Else():
+                m.sync += [
+                tot.eq(b_m - a_m),
+                z_s.eq(b_s)]
         return m
 
 """