From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 17:53:13 +0000 (+0100)
Subject: oops forgot to switch write-enable off
X-Git-Tag: div_pipeline~589
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=272a0021e429a04186b5771d32e5b409826b3810;p=soc.git

oops forgot to switch write-enable off
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index c1bbf743..ed688a48 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -164,6 +164,8 @@ class NonProductionCore(Elaboratable):
                 # will the write-enable be activated
                 with m.If(wrpick.en_o):
                     sync += wport.wen.eq(write)
+                with m.Else():
+                    sync += wport.wen.eq(0)
 
                 # connect up the FU req/go signals and the reg-read to the FU
                 # these are arbitrated by Data.ok signals