From: Marek Olšák <marek.olsak@amd.com>
Date: Thu, 27 Oct 2016 21:48:44 +0000 (+0200)
Subject: radeonsi/gfx9: do DCC clears on non-mipmapped textures only
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=272b50a6f43adc6aa49da778119af9b219c170ae;p=mesa.git

radeonsi/gfx9: do DCC clears on non-mipmapped textures only

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 1838de4f4d4..5b1f941521b 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2417,7 +2417,7 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
 			unsigned level, unsigned clear_value)
 {
 	struct pipe_resource *dcc_buffer;
-	uint64_t dcc_offset;
+	uint64_t dcc_offset, clear_size;
 
 	assert(rtex->dcc_offset && level < rtex->surface.num_dcc_levels);
 
@@ -2429,10 +2429,18 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
 		dcc_offset = rtex->dcc_offset;
 	}
 
-	dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
+	if (rctx->chip_class >= GFX9) {
+		/* Mipmap level clears aren't implemented. */
+		assert(rtex->resource.b.b.last_level == 0);
+		/* MSAA needs a different clear size. */
+		assert(rtex->resource.b.b.nr_samples <= 1);
+		clear_size = rtex->surface.dcc_size;
+	} else {
+		dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
+		clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size;
+	}
 
-	rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset,
-			   rtex->surface.u.legacy.level[level].dcc_fast_clear_size,
+	rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset, clear_size,
 			   clear_value, R600_COHERENCY_CB_META);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index da6c0cda2bb..24c73d0e8de 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1035,6 +1035,11 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 		 */
 		if (dst->dcc_offset &&
 		    info->dst.level < dst->surface.num_dcc_levels) {
+			/* TODO: Implement per-level DCC clears for GFX9. */
+			if (sctx->b.chip_class >= GFX9 &&
+			    info->dst.resource->last_level != 0)
+				goto resolve_to_temp;
+
 			vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
 					   0xFFFFFFFF);
 			dst->dirty_level_mask &= ~(1 << info->dst.level);