From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 1 Apr 2020 16:08:45 +0000 (-0400)
Subject: Add test for sin_cos_pipe (not working still)
X-Git-Tag: ls180-24jan2020~102
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=272c668bdf2bc20b575fd10cd8b295f2811ce92b;p=ieee754fpu.git

Add test for sin_cos_pipe (not working still)
---

diff --git a/src/ieee754/cordic/pipe_data.py b/src/ieee754/cordic/pipe_data.py
index 6335244f..a284bff1 100644
--- a/src/ieee754/cordic/pipe_data.py
+++ b/src/ieee754/cordic/pipe_data.py
@@ -1,4 +1,5 @@
 from nmigen import Signal, Const
+from nmutil.dynamicpipe import DynamicPipe, SimpleHandshakeRedir
 import math
 
 class CordicInitialData:
@@ -11,7 +12,7 @@ class CordicInitialData:
         yield from self.z
 
     def eq(self, i):
-        return [self.z.eq(i.z)]
+        return [self.z0.eq(i.z0)]
 
 class CordicData:
 
@@ -40,3 +41,6 @@ class CordicPipeSpec:
         self.ZMAX = int(round(self.M * math.pi/2))
         zm = Const(-self.ZMAX)
         self.iterations = zm.width - 1
+
+        self.pipekls = SimpleHandshakeRedir
+        self.stage = None
diff --git a/src/ieee754/cordic/sin_cos_pipe_stage.py b/src/ieee754/cordic/sin_cos_pipe_stage.py
index dcf9e4bc..924a099e 100644
--- a/src/ieee754/cordic/sin_cos_pipe_stage.py
+++ b/src/ieee754/cordic/sin_cos_pipe_stage.py
@@ -8,10 +8,10 @@ class CordicInitialStage(PipeModBase):
         super().__init__(pspec, "cordicinit")
 
     def ispec(self):
-        return CordicInitialData(self.pspec, False)
+        return CordicInitialData(self.pspec)
 
     def ospec(self):
-        return CordicData(self.pspec, False)
+        return CordicData(self.pspec)
 
     def elaborate(self, platform):
         m = Module()
@@ -35,10 +35,10 @@ class CordicStage(PipeModBase):
         self.stagenum = stagenum
 
     def ispec(self):
-        return CordicData(self.pspec, False)
+        return CordicData(self.pspec)
 
     def ospec(self):
-        return CordicData(self.pspec, False)
+        return CordicData(self.pspec)
 
     def elaborate(self, platform):
         m = Module()
diff --git a/src/ieee754/cordic/sin_cos_pipeline.py b/src/ieee754/cordic/sin_cos_pipeline.py
index 463f9603..65ac9525 100644
--- a/src/ieee754/cordic/sin_cos_pipeline.py
+++ b/src/ieee754/cordic/sin_cos_pipeline.py
@@ -1,25 +1,30 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
+from nmutil.pipemodbase import PipeModBaseChain
 
-from ieee754.cordic.sin_cos_pipe_stages import (
+from ieee754.cordic.sin_cos_pipe_stage import (
     CordicStage, CordicInitialStage)
 from ieee754.cordic.pipe_data import (CordicPipeSpec, CordicData,
-                                      CordicInitalData)
+                                      CordicInitialData)
+
+class CordicPipeChain(PipeModBaseChain):
+    def get_chain(self):
+        initstage = CordicInitialStage(self.pspec)
+        cordicstages = []
+        for i in range(self.pspec.iterations):
+            stage = CordicStage(self.pspec, i)
+            cordicstages.append(stage)
+        return [initstage] + cordicstages
+        
 
 class CordicBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
-        self.init = CordicInitialStage(pspec)
-        self.cordicstages = []
-        for i in range(pspec.iterations):
-            stage = CordicStage(pspec, i)
-            self.cordicstages.append(stage)
-        self._eqs = self.connect([self.init] + self.cordicstages)
+        self.chain = CordicPipeChain(pspec)
+        self._eqs = self.connect([self.chain])
         
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.init = self.init
-        for i, stage in enumerate(self.cordicstages):
-            setattr(m.submodules, "stage%d" % i, stage)
+        m.submodules.chain = self.chain
         m.d.comb += self._eqs
         return m
diff --git a/src/ieee754/cordic/test/test_pipe.py b/src/ieee754/cordic/test/test_pipe.py
new file mode 100644
index 00000000..8e8bbc9f
--- /dev/null
+++ b/src/ieee754/cordic/test/test_pipe.py
@@ -0,0 +1,43 @@
+from nmigen import Module, Signal
+from nmigen.back.pysim import Simulator, Delay
+from nmigen.test.utils import FHDLTestCase
+
+from ieee754.cordic.sin_cos_pipeline import CordicBasePipe
+from ieee754.cordic.pipe_data import CordicPipeSpec
+from python_sin_cos import run_cordic
+import unittest
+
+
+class SinCosTestCase(FHDLTestCase):
+    def run_test(self, zin=0, fracbits=8, expected_sin=0, expected_cos=0):
+        m = Module()
+        pspec = CordicPipeSpec(fracbits=fracbits)
+        m.submodules.dut = dut = CordicBasePipe(pspec)
+
+        z = Signal(dut.p.data_i.z0.shape())
+        x = Signal(dut.n.data_o.x.shape())
+        y = Signal(dut.n.data_o.y.shape())
+
+        sim = Simulator(m)
+        sim.add_clock(1e-6)
+
+        def process():
+            yield z.eq(zin)
+            for i in range(10):
+                yield
+        sim.add_sync_process(process)
+        with sim.write_vcd("pipeline.vcd", "pipeline.gtkw", traces=[
+                z, x, y]):
+            sim.run()
+
+    def run_test_assert(self, z, fracbits=8):
+        (sin, cos) = run_cordic(z, fracbits=fracbits, log=False)
+        self.run_test(zin=z, fracbits=fracbits,
+                      expected_sin=sin, expected_cos=cos)
+
+    def test_0(self):
+        self.run_test_assert(0)
+
+
+if __name__ == "__main__":
+    unittest.main()