From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Fri, 19 Oct 2018 15:40:57 +0000 (+0200)
Subject: rs6000: Put CR0 first in REG_ALLOC_ORDER
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=273f3d4bb4734845ce527bf92b4781e288e4aae2;p=gcc.git

rs6000: Put CR0 first in REG_ALLOC_ORDER

IRA and LRA prefer to use CR7 (which is first in REG_ALLOC_ORDER) over
CR0, although the latter often is cheaper ("x" vs. "y" constraints).
We should figure out why this is and fix it; but until that is done,
this patch makes CR0 the first allocated register: it improves the
current code, and it is required for later patches to be effective.

(It changes two testcases to no longer look at what CR field is
allocated).


	* config/rs6000/rs6000.h (REG_ALLOC_ORDER): Move 68 (that is, CR0) to
	be the first CR field allocated.

gcc/testsuite/
	* gcc.target/powerpc/safe-indirect-jump-2.c: Do not check assigned CR
	field number.
	* gcc.target/powerpc/safe-indirect-jump-3.c: Ditto.

From-SVN: r265318
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 082ef49dcb0..970f72a5676 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-19  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000.h (REG_ALLOC_ORDER): Move 68 (that is, CR0) to
+	be the first CR field allocated.
+
 2018-10-19  Richard Biener  <rguenther@suse.de>
 
 	PR target/87657
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 86a7fb83bd8..4ab027ca3ea 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -952,7 +952,7 @@ enum data_align { align_abi, align_opt, align_both };
    33,								\
    63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51,		\
    50, 49, 48, 47, 46,						\
-   75, 73, 74, 69, 68, 72, 71, 70,				\
+   68, 75, 73, 74, 69, 72, 71, 70,				\
    MAYBE_R2_AVAILABLE						\
    9, 10, 8, 7, 6, 5, 4,					\
    3, EARLY_R12 11, 0,						\
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 45b9bce96fe..80c0b4b01ba 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-19  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* gcc.target/powerpc/safe-indirect-jump-2.c: Do not check assigned CR
+	field number.
+	* gcc.target/powerpc/safe-indirect-jump-3.c: Ditto.
+
 2018-10-19  Richard Biener  <rguenther@suse.de>
 
 	PR middle-end/87645
diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
index d3d040fbbf0..d6fc6a3e0b7 100644
--- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
@@ -27,8 +27,6 @@ int foo (int x)
   return spaz (x) / 2;
 }
 
-/* The following assumes CR7 as the first chosen volatile.  */
-
-/* { dg-final { scan-assembler "crset 30" } } */
-/* { dg-final { scan-assembler "beqctr- 7" } } */
+/* { dg-final { scan-assembler "crset" } } */
+/* { dg-final { scan-assembler "beqctr-" } } */
 /* { dg-final { scan-assembler {b \$} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
index c338e30d01a..87881fb18fc 100644
--- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
@@ -46,8 +46,6 @@ int foo (int x)
   return a;
 }
 
-/* The following assumes CR7 as the first chosen volatile.  */
-
-/* { dg-final { scan-assembler "crset 30" } } */
-/* { dg-final { scan-assembler "beqctr- 7" } } */
+/* { dg-final { scan-assembler "crset" } } */
+/* { dg-final { scan-assembler "beqctr-" } } */
 /* { dg-final { scan-assembler {b \$} } } */