From: lkcl <lkcl@web>
Date: Wed, 20 Jul 2022 15:33:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1155
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27479d16b4e2ca08dbf1e6e9f51129a4fc38e836;p=libreriscv.git

---

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 2e1e54466..d1067448b 100644
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -35,7 +35,7 @@ Scalar instructions added as part of [[sv/svp64]] development, these are
 all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
 on Simple-V).
 Explanation of the rules for twin register targets
-(implicit RS, FRS) explained in SVPY4 [[sv/svp64/appendix]]
+(implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
 
 * [[isa/svfixedload]] DEPRECATED, do not use.
 * [[isa/svfixedarith]]