From: Marek Olšák <marek.olsak@amd.com>
Date: Fri, 27 Dec 2013 18:14:55 +0000 (+0100)
Subject: radeonsi: disable HTILE for 1D-tiled depth-stencil buffers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2748b7da7e2a65bc46d12187b27585902a88f0aa;p=mesa.git

radeonsi: disable HTILE for 1D-tiled depth-stencil buffers

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
---

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index c7ef2777c20..caf3743e72f 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -466,6 +466,11 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
 	unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
 	unsigned num_pipes = rscreen->tiling_info.num_channels;
 
+	/* HTILE doesn't work with 1D tiling (there's massive corruption
+	 * in glxgears). */
+	if (rtex->surface.level[0].mode != RADEON_SURF_MODE_2D)
+		return 0;
+
 	switch (num_pipes) {
 	case 2:
 		cl_width = 32;