From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 4 Aug 2012 14:32:15 +0000 (+0200)
Subject: bios: asmiprobe command
X-Git-Tag: 24jan2021_ls180~3091
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=274a00217ec9f491cc1444fa49328f46ba266250;p=litex.git

bios: asmiprobe command

Because with reordering architectures come order-dependent intermittent bugs.
---

diff --git a/software/bios/Makefile b/software/bios/Makefile
index 42aa7bfe..827fe207 100644
--- a/software/bios/Makefile
+++ b/software/bios/Makefile
@@ -1,7 +1,7 @@
 M2DIR=../..
 include $(M2DIR)/software/common.mak
 
-OBJECTS=crt0.o isr.o ddrinit.o main.o microudp.o tftp.o boot-helper.o boot.o dataflow.o
+OBJECTS=crt0.o isr.o sdram.o main.o microudp.o tftp.o boot-helper.o boot.o dataflow.o
 
 all: bios.bin
 
diff --git a/software/bios/ddrinit.c b/software/bios/ddrinit.c
deleted file mode 100644
index ce53f050..00000000
--- a/software/bios/ddrinit.c
+++ /dev/null
@@ -1,198 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <hw/dfii.h>
-#include <hw/mem.h>
-
-#include "ddrinit.h"
-
-static void cdelay(int i)
-{
-	while(i > 0) {
-		__asm__ volatile("nop");
-		i--;
-	}
-}
-
-static void setaddr(int a)
-{
-	CSR_DFII_AH_P0 = (a & 0xff00) >> 8;
-	CSR_DFII_AL_P0 = a & 0x00ff;
-	CSR_DFII_AH_P1 = (a & 0xff00) >> 8;
-	CSR_DFII_AL_P1 = a & 0x00ff;
-}
-
-static void init_sequence(void)
-{
-	int i;
-	
-	/* Bring CKE high */
-	setaddr(0x0000);
-	CSR_DFII_BA_P0 = 0;
-	CSR_DFII_CONTROL = DFII_CONTROL_CKE;
-	
-	/* Precharge All */
-	setaddr(0x0400);
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
-	
-	/* Load Extended Mode Register */
-	CSR_DFII_BA_P0 = 1;
-	setaddr(0x0000);
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
-	CSR_DFII_BA_P0 = 0;
-	
-	/* Load Mode Register */
-	setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
-	cdelay(200);
-	
-	/* Precharge All */
-	setaddr(0x0400);
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
-	
-	/* 2x Auto Refresh */
-	for(i=0;i<2;i++) {
-		setaddr(0);
-		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS;
-		cdelay(4);
-	}
-	
-	/* Load Mode Register */
-	setaddr(0x0032); /* CL=3, BL=4 */
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
-	cdelay(200);
-}
-
-void ddrsw(void)
-{
-	CSR_DFII_CONTROL = DFII_CONTROL_CKE;
-	printf("DDR now under software control\n");
-}
-
-void ddrhw(void)
-{
-	CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
-	printf("DDR now under hardware control\n");
-}
-
-void ddrrow(char *_row)
-{
-	char *c;
-	unsigned int row;
-	
-	if(*_row == 0) {
-		setaddr(0x0000);
-		CSR_DFII_BA_P0 = 0;
-		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
-		cdelay(15);
-		printf("Precharged\n");
-	} else {
-		row = strtoul(_row, &c, 0);
-		if(*c != 0) {
-			printf("incorrect row\n");
-			return;
-		}
-		setaddr(row);
-		CSR_DFII_BA_P0 = 0;
-		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CS;
-		cdelay(15);
-		printf("Activated row %d\n", row);
-	}
-}
-
-void ddrrd(char *startaddr)
-{
-	char *c;
-	unsigned int addr;
-	int i;
-
-	if(*startaddr == 0) {
-		printf("ddrrd <address>\n");
-		return;
-	}
-	addr = strtoul(startaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect address\n");
-		return;
-	}
-	
-	setaddr(addr);
-	CSR_DFII_BA_P0 = 0;
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA;
-	cdelay(15);
-	
-	for(i=0;i<8;i++)
-		printf("%02x", MMPTR(0xe0000834+4*i));
-	for(i=0;i<8;i++)
-		printf("%02x", MMPTR(0xe0000884+4*i));
-	printf("\n");
-}
-
-void ddrwr(char *startaddr)
-{
-	char *c;
-	unsigned int addr;
-	int i;
-
-	if(*startaddr == 0) {
-		printf("ddrrd <address>\n");
-		return;
-	}
-	addr = strtoul(startaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect address\n");
-		return;
-	}
-	
-	for(i=0;i<8;i++) {
-		MMPTR(0xe0000814+4*i) = i;
-		MMPTR(0xe0000864+4*i) = 0xf0 + i;
-	}
-	
-	setaddr(addr);
-	CSR_DFII_BA_P1 = 0;
-	CSR_DFII_COMMAND_P1 = DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA;
-}
-
-#define TEST_SIZE (4*1024*1024)
-
-int memtest_silent(void)
-{
-	volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
-	int i;
-	unsigned int prv;
-	
-	prv = 0;
-	for(i=0;i<TEST_SIZE/4;i++) {
-		prv = 1664525*prv + 1013904223;
-		array[i] = prv;
-	}
-	
-	prv = 0;
-	for(i=0;i<TEST_SIZE/4;i++) {
-		prv = 1664525*prv + 1013904223;
-		if(array[i] != prv)
-			return 0;
-	}
-	return 1;
-}
-
-void memtest(void)
-{
-	if(memtest_silent())
-		printf("OK\n");
-	else
-		printf("Failed\n");
-}
-
-int ddrinit(void)
-{
-	printf("Initializing DDR SDRAM...\n");
-	
-	init_sequence();
-	CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
-	if(!memtest_silent())
-		return 0;
-	
-	return 1;
-}
diff --git a/software/bios/ddrinit.h b/software/bios/ddrinit.h
deleted file mode 100644
index 32d157ae..00000000
--- a/software/bios/ddrinit.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __DDRINIT_H
-#define __DDRINIT_H
-
-void ddrsw(void);
-void ddrhw(void);
-void ddrrow(char *_row);
-void ddrrd(char *startaddr);
-void ddrwr(char *startaddr);
-int memtest_silent(void);
-void memtest(void);
-int ddrinit(void);
-
-#endif /* __DDRINIT_H */
diff --git a/software/bios/main.c b/software/bios/main.c
index 30cd8718..606ba8c6 100644
--- a/software/bios/main.c
+++ b/software/bios/main.c
@@ -13,7 +13,7 @@
 #include <hw/mem.h>
 #include <hw/minimac.h>
 
-#include "ddrinit.h"
+#include "sdram.h"
 #include "dataflow.h"
 #include "boot.h"
 
@@ -367,6 +367,7 @@ static void do_command(char *c)
 	else if(strcmp(token, "ddrwr") == 0) ddrwr(get_token(&c));
 	else if(strcmp(token, "memtest") == 0) memtest();
 	else if(strcmp(token, "ddrinit") == 0) ddrinit();
+	else if(strcmp(token, "asmiprobe") == 0) asmiprobe();
 	
 	else if(strcmp(token, "dfs") == 0) dfs(get_token(&c));
 
diff --git a/software/bios/sdram.c b/software/bios/sdram.c
new file mode 100644
index 00000000..233d1912
--- /dev/null
+++ b/software/bios/sdram.c
@@ -0,0 +1,228 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <hw/dfii.h>
+#include <hw/mem.h>
+#include <csrbase.h>
+
+#include "sdram.h"
+
+static void cdelay(int i)
+{
+	while(i > 0) {
+		__asm__ volatile("nop");
+		i--;
+	}
+}
+
+static void setaddr(int a)
+{
+	CSR_DFII_AH_P0 = (a & 0xff00) >> 8;
+	CSR_DFII_AL_P0 = a & 0x00ff;
+	CSR_DFII_AH_P1 = (a & 0xff00) >> 8;
+	CSR_DFII_AL_P1 = a & 0x00ff;
+}
+
+static void init_sequence(void)
+{
+	int i;
+	
+	/* Bring CKE high */
+	setaddr(0x0000);
+	CSR_DFII_BA_P0 = 0;
+	CSR_DFII_CONTROL = DFII_CONTROL_CKE;
+	
+	/* Precharge All */
+	setaddr(0x0400);
+	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
+	
+	/* Load Extended Mode Register */
+	CSR_DFII_BA_P0 = 1;
+	setaddr(0x0000);
+	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
+	CSR_DFII_BA_P0 = 0;
+	
+	/* Load Mode Register */
+	setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
+	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
+	cdelay(200);
+	
+	/* Precharge All */
+	setaddr(0x0400);
+	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
+	
+	/* 2x Auto Refresh */
+	for(i=0;i<2;i++) {
+		setaddr(0);
+		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS;
+		cdelay(4);
+	}
+	
+	/* Load Mode Register */
+	setaddr(0x0032); /* CL=3, BL=4 */
+	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
+	cdelay(200);
+}
+
+void ddrsw(void)
+{
+	CSR_DFII_CONTROL = DFII_CONTROL_CKE;
+	printf("DDR now under software control\n");
+}
+
+void ddrhw(void)
+{
+	CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
+	printf("DDR now under hardware control\n");
+}
+
+void ddrrow(char *_row)
+{
+	char *c;
+	unsigned int row;
+	
+	if(*_row == 0) {
+		setaddr(0x0000);
+		CSR_DFII_BA_P0 = 0;
+		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
+		cdelay(15);
+		printf("Precharged\n");
+	} else {
+		row = strtoul(_row, &c, 0);
+		if(*c != 0) {
+			printf("incorrect row\n");
+			return;
+		}
+		setaddr(row);
+		CSR_DFII_BA_P0 = 0;
+		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CS;
+		cdelay(15);
+		printf("Activated row %d\n", row);
+	}
+}
+
+void ddrrd(char *startaddr)
+{
+	char *c;
+	unsigned int addr;
+	int i;
+
+	if(*startaddr == 0) {
+		printf("ddrrd <address>\n");
+		return;
+	}
+	addr = strtoul(startaddr, &c, 0);
+	if(*c != 0) {
+		printf("incorrect address\n");
+		return;
+	}
+	
+	setaddr(addr);
+	CSR_DFII_BA_P0 = 0;
+	CSR_DFII_COMMAND_P0 = DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA;
+	cdelay(15);
+	
+	for(i=0;i<8;i++)
+		printf("%02x", MMPTR(0xe0000834+4*i));
+	for(i=0;i<8;i++)
+		printf("%02x", MMPTR(0xe0000884+4*i));
+	printf("\n");
+}
+
+void ddrwr(char *startaddr)
+{
+	char *c;
+	unsigned int addr;
+	int i;
+
+	if(*startaddr == 0) {
+		printf("ddrrd <address>\n");
+		return;
+	}
+	addr = strtoul(startaddr, &c, 0);
+	if(*c != 0) {
+		printf("incorrect address\n");
+		return;
+	}
+	
+	for(i=0;i<8;i++) {
+		MMPTR(0xe0000814+4*i) = i;
+		MMPTR(0xe0000864+4*i) = 0xf0 + i;
+	}
+	
+	setaddr(addr);
+	CSR_DFII_BA_P1 = 0;
+	CSR_DFII_COMMAND_P1 = DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA;
+}
+
+#define TEST_SIZE (4*1024*1024)
+
+int memtest_silent(void)
+{
+	volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
+	int i;
+	unsigned int prv;
+	
+	prv = 0;
+	for(i=0;i<TEST_SIZE/4;i++) {
+		prv = 1664525*prv + 1013904223;
+		array[i] = prv;
+	}
+	
+	prv = 0;
+	for(i=0;i<TEST_SIZE/4;i++) {
+		prv = 1664525*prv + 1013904223;
+		if(array[i] != prv)
+			return 0;
+	}
+	return 1;
+}
+
+void memtest(void)
+{
+	if(memtest_silent())
+		printf("OK\n");
+	else
+		printf("Failed\n");
+}
+
+int ddrinit(void)
+{
+	printf("Initializing DDR SDRAM...\n");
+	
+	init_sequence();
+	CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
+	if(!memtest_silent())
+		return 0;
+	
+	return 1;
+}
+
+static const char *format_slot_state(int state)
+{
+	switch(state) {
+		case 0: return "Empty";
+		case 1: return "Pending";
+		case 2: return "Processing";
+		default: return "UNEXPECTED VALUE";
+	}
+}
+
+void asmiprobe(void)
+{
+	volatile unsigned int *regs = (unsigned int *)ASMIPROBE_BASE;
+	int slot_count;
+	int trace_depth;
+	int i;
+	int offset;
+	
+	offset = 0;
+	slot_count = regs[offset++];
+	trace_depth = regs[offset++];
+	for(i=0;i<slot_count;i++)
+		printf("Slot #%d: %s\n", i, format_slot_state(regs[offset++]));
+	printf("Latest tags:\n");
+	for(i=0;i<trace_depth;i++)
+		printf("%d ", regs[offset++]);
+	printf("\n");
+}
diff --git a/software/bios/sdram.h b/software/bios/sdram.h
new file mode 100644
index 00000000..d48fcf93
--- /dev/null
+++ b/software/bios/sdram.h
@@ -0,0 +1,15 @@
+#ifndef __SDRAM_H
+#define __SDRAM_H
+
+void ddrsw(void);
+void ddrhw(void);
+void ddrrow(char *_row);
+void ddrrd(char *startaddr);
+void ddrwr(char *startaddr);
+int memtest_silent(void);
+void memtest(void);
+int ddrinit(void);
+
+void asmiprobe(void);
+
+#endif /* __SDRAM_H */