From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jul 2014 10:10:57 +0000 (+0200)
Subject: Fixed RTLIL::SigSpec::append_bit() for appending constants
X-Git-Tag: yosys-0.4~560
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=274c51487937e3ca37c3520e98e996cb5918e982;p=yosys.git

Fixed RTLIL::SigSpec::append_bit() for appending constants
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index c4c08d5b8..c232dadd2 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1716,9 +1716,10 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
 		chunks.push_back(bit);
 	else
 		if (bit.wire == NULL)
-			if (chunks.back().wire == NULL)
+			if (chunks.back().wire == NULL) {
 				chunks.back().data.bits.push_back(bit.data);
-			else
+				chunks.back().width++;
+			} else
 				chunks.push_back(bit);
 		else
 			if (chunks.back().wire == bit.wire && chunks.back().offset + chunks.back().width == bit.offset)