From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 11:42:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2334
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=274cab2ecd1a0c0ba3620789cbab7ab30510bb7d;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index e92228cb1..f64d893d2 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -400,7 +400,8 @@ ISA, the amount of data processing requested
 and controlled by each instruction is enormous, and leaves the
 Decode and Issue Engines idle, as well as the L1 I-Cache. With
 programs being smaller, chances are higher that they fit into
-L1 Cache, or that the L1 Cache may be made smaller.
+L1 Cache, or that the L1 Cache may be made smaller: either way
+is a considerable O(N^2) power-saving.
 
 Even a Packed SIMD ISA could take limited advantage of a higher
 bang-per-buck for limited specific workloads, as long as the