From: lkcl <lkcl@web>
Date: Fri, 10 Jun 2022 10:24:45 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1875
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=274e3c819f2a370e30a45cf6c3b8746e568bf979;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index bb163869d..2eed126e8 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -276,7 +276,7 @@ through the Power ISA WG Process). It would
 be similar to deciding that `add` should be changed from X-Form
 to D-Form.
 
-# Single Predication
+# Single Predication <a name="1p"> </a>
 
 This is a standard mode normally found in Vector ISAs.  every element in every source Vector and in the destination uses the same bit of one single predicate mask.
 
@@ -338,7 +338,7 @@ The following schedule for srcstep and dststep will occur:
 
 Here, both srcstep and dststep remain in lockstep because sz=dz=1
 
-# Twin Predication
+# Twin Predication <a name="2p"> </a>
 
 This is a novel concept that allows predication to be applied to a single
 source and a single dest register.  The following types of traditional