From: Jacob Lifshay Date: Wed, 29 Jul 2020 00:26:16 +0000 (-0700) Subject: format some tests X-Git-Tag: semi_working_ecp5~503 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2752f24d27389fb3e66c4c5d10624eb1eea044c1;p=soc.git format some tests --- diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index dd60d062..4af953d8 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -119,9 +119,9 @@ def tst_config_pi(testcls, ifacetype): reg_wid=64) cmpi = ConfigMemoryPortInterface(pspec) dut.submodules.pi = cmpi.pi - if hasattr(cmpi, 'lsmem'): # hmmm not happy about this + if hasattr(cmpi, 'lsmem'): # hmmm not happy about this dut.submodules.lsmem = cmpi.lsmem.lsi - vl = rtlil.convert(dut, ports=[])#dut.ports()) + vl = rtlil.convert(dut, ports=[]) # dut.ports()) with open("test_pi_%s.il" % ifacetype, "w") as f: f.write(vl) @@ -143,4 +143,3 @@ class TestPIMem(unittest.TestCase): if __name__ == '__main__': unittest.main(exit=False) - diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 7c20f0e9..4cdd276f 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -63,17 +63,18 @@ class DualPortSplitter(Elaboratable): PortInterface *may* need to be changed so that the length is a binary number (accepting values 1-16). """ + def __init__(self): self.outp = [PortInterface(name="outp_0"), PortInterface(name="outp_1")] - self.inp = PortInterface(name="inp") + self.inp = PortInterface(name="inp") print(self.outp) def elaborate(self, platform): m = Module() comb = m.d.comb m.submodules.splitter = splitter = LDSTSplitter(64, 48, 4) - comb += splitter.addr_i.eq(self.inp.addr) #XXX + comb += splitter.addr_i.eq(self.inp.addr) # XXX #comb += splitter.len_i.eq() #comb += splitter.valid_i.eq() comb += splitter.is_ld_i.eq(self.inp.is_ld_i) @@ -147,13 +148,13 @@ class DataMerger(Elaboratable): def elaborate(self, platform): m = Module() comb = m.d.comb - #(1) pick a row + # (1) pick a row m.submodules.pick = pick = PriorityEncoder(self.array_size) for j in range(self.array_size): comb += pick.i[j].eq(self.addr_array_i[j].bool()) valid = ~pick.n idx = pick.o - #(2) merge + # (2) merge with m.If(valid): l = [] for j in range(self.array_size): @@ -162,8 +163,8 @@ class DataMerger(Elaboratable): with m.If(select): comb += r.eq(self.data_i[j]) l.append(r) - comb += self.data_o.data.eq(ortreereduce(l,"data")) - comb += self.data_o.en.eq(ortreereduce(l,"en")) + comb += self.data_o.data.eq(ortreereduce(l, "data")) + comb += self.data_o.en.eq(ortreereduce(l, "en")) return m @@ -202,7 +203,7 @@ class L0CacheBuffer(Elaboratable): comb, sync = m.d.comb, m.d.sync # connect the ports as modules - #for i in range(self.n_units): + # for i in range(self.n_units): # setattr(m.submodules, "port%d" % i, self.dports[i]) # state-machine latches @@ -218,8 +219,8 @@ class L0CacheBuffer(Elaboratable): ldsti = [] for i in range(self.n_units): pi = self.dports[i] - busy = (pi.is_ld_i | pi.is_st_i)# & pi.busy_o - ldsti.append(busy) # accumulate ld/st-req + busy = (pi.is_ld_i | pi.is_st_i) # & pi.busy_o + ldsti.append(busy) # accumulate ld/st-req # put the requests into the priority-picker comb += pick.i.eq(Cat(*ldsti)) @@ -245,7 +246,7 @@ class L0CacheBuffer(Elaboratable): with m.If(idx_l.q): comb += self.pimem.connect_port(port) with m.If(~self.pimem.pi.busy_o): - comb += reset_l.s.eq(1) # reset when no longer busy + comb += reset_l.s.eq(1) # reset when no longer busy # ugly hack, due to simultaneous addr req-go acknowledge reset_delay = Signal(reset_less=True) @@ -269,13 +270,13 @@ class TstL0CacheBuffer(Elaboratable): addrwid = pspec.addr_wid self.cmpi = ConfigMemoryPortInterface(pspec) self.pimem = self.cmpi.pi - self.l0 = L0CacheBuffer(n_units, self.pimem, regwid, addrwid<<1) + self.l0 = L0CacheBuffer(n_units, self.pimem, regwid, addrwid << 1) def elaborate(self, platform): m = Module() m.submodules.pimem = self.pimem m.submodules.l0 = self.l0 - if hasattr(self.cmpi, 'lsmem'): # hmmm not happy about this + if hasattr(self.cmpi, 'lsmem'): # hmmm not happy about this m.submodules.lsmem = self.cmpi.lsmem.lsi return m @@ -328,7 +329,7 @@ def l0_cache_ldst(arg, dut): def data_merger_merge(dut): print("data_merger") - #starting with all inputs zero + # starting with all inputs zero yield Settle() en = yield dut.data_o.en data = yield dut.data_o.data @@ -358,7 +359,7 @@ class TestL0Cache(unittest.TestCase): mask_wid=8, reg_wid=64) dut = TstL0CacheBuffer(pspec) - vl = rtlil.convert(dut, ports=[])# TODOdut.ports()) + vl = rtlil.convert(dut, ports=[]) # TODOdut.ports()) with open("test_basic_l0_cache_bare_wb.il", "w") as f: f.write(vl) @@ -372,7 +373,7 @@ class TestL0Cache(unittest.TestCase): mask_wid=8, reg_wid=64) dut = TstL0CacheBuffer(pspec) - vl = rtlil.convert(dut, ports=[])# TODOdut.ports()) + vl = rtlil.convert(dut, ports=[]) # TODOdut.ports()) with open("test_basic_l0_cache.il", "w") as f: f.write(vl) @@ -386,7 +387,7 @@ class TestDataMerger(unittest.TestCase): dut = DataMerger(8) #vl = rtlil.convert(dut, ports=dut.ports()) - #with open("test_data_merger.il", "w") as f: + # with open("test_data_merger.il", "w") as f: # f.write(vl) run_simulation(dut, data_merger_merge(dut), @@ -399,13 +400,12 @@ class TestDualPortSplitter(unittest.TestCase): dut = DualPortSplitter() #vl = rtlil.convert(dut, ports=dut.ports()) - #with open("test_data_merger.il", "w") as f: + # with open("test_data_merger.il", "w") as f: # f.write(vl) - #run_simulation(dut, data_merger_merge(dut), + # run_simulation(dut, data_merger_merge(dut), # vcd_name='test_dual_port_splitter.vcd') if __name__ == '__main__': unittest.main(exit=False) - diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 92ddc445..118653d2 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -140,7 +140,7 @@ class ALUTestCase(TestAccumulatorBase): xer[XER_bits['CA']] = 1 initial_sprs[special_sprs['XER']] = xer self.add_case(Program(lst, bigendian), - initial_regs, initial_sprs) + initial_regs, initial_sprs) def case_cmp(self): lst = ["subf. 1, 6, 7", diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index a9b7cc0b..32e79506 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -102,8 +102,8 @@ class BranchTestCase(TestAccumulatorBase): lst = [f"bc {bo}, {bi}, {bc}"] initial_sprs = {9: SelectableInt(ctr, 64)} self.add_case(Program(lst, bigendian), - initial_sprs=initial_sprs, - initial_cr=cr) + initial_sprs=initial_sprs, + initial_cr=cr) def case_bc_reg(self): # XXX: bcctr and bcctrl time out (irony: they're counters) @@ -122,8 +122,8 @@ class BranchTestCase(TestAccumulatorBase): 8: SelectableInt(lr, 64), 815: SelectableInt(tar, 64)} self.add_case(Program(lst, bigendian), - initial_sprs=initial_sprs, - initial_cr=cr) + initial_sprs=initial_sprs, + initial_cr=cr) def case_ilang(self): pspec = BranchPipeSpec(id_wid=2) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 904fc5e7..9f2a47b1 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -78,7 +78,7 @@ class CRTestCase(TestAccumulatorBase): initial_regs = [0] * 32 initial_regs[2] = random.randint(0, (1 << 32)-1) self.add_case(Program(lst, bigendian), initial_regs=initial_regs, - initial_cr=cr) + initial_cr=cr) def case_mtocrf(self): for i in range(20): @@ -88,7 +88,7 @@ class CRTestCase(TestAccumulatorBase): initial_regs = [0] * 32 initial_regs[2] = random.randint(0, (1 << 32)-1) self.add_case(Program(lst, bigendian), initial_regs=initial_regs, - initial_cr=cr) + initial_cr=cr) def case_mfcr(self): for i in range(5): @@ -114,7 +114,7 @@ class CRTestCase(TestAccumulatorBase): #initial_regs[2] = i*2 #initial_regs[3] = i*2+1 self.add_case(Program(lst, bigendian), - initial_regs=initial_regs, initial_cr=cr) + initial_regs=initial_regs, initial_cr=cr) def case_setb(self): for i in range(20): diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index f2f5b705..b7ea7b4e 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -78,7 +78,7 @@ class TrapTestCase(TestAccumulatorBase): initial_regs[1] = 1 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} self.add_case(Program(lst, bigendian), - initial_regs, initial_sprs) + initial_regs, initial_sprs) def case_0_trap_eq_imm(self): insns = ["twi", "tdi"] @@ -129,7 +129,7 @@ class TrapTestCase(TestAccumulatorBase): initial_regs[1] = 0xffffffffffffffff msr = 1 << MSR.PR # set in "problem state" self.add_case(Program(lst, bigendian), initial_regs, - initial_msr=msr) + initial_msr=msr) def case_7_rfid_priv_0(self): lst = ["rfid"] @@ -138,22 +138,22 @@ class TrapTestCase(TestAccumulatorBase): initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} msr = 1 << MSR.PR # set in "problem state" self.add_case(Program(lst, bigendian), - initial_regs, initial_sprs, - initial_msr=msr) + initial_regs, initial_sprs, + initial_msr=msr) def case_8_mfmsr(self): lst = ["mfmsr 1"] initial_regs = [0] * 32 msr = (~(1 << MSR.PR)) & 0xffffffffffffffff self.add_case(Program(lst, bigendian), initial_regs, - initial_msr=msr) + initial_msr=msr) def case_9_mfmsr_priv(self): lst = ["mfmsr 1"] initial_regs = [0] * 32 msr = 1 << MSR.PR # set in "problem state" self.add_case(Program(lst, bigendian), initial_regs, - initial_msr=msr) + initial_msr=msr) def case_999_illegal(self): # ok, um this is a bit of a cheat: use an instruction we know diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 58742863..b8276002 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -44,9 +44,9 @@ def setup_i_memory(imem, startaddr, instructions): for i in range(mem.depth): yield mem._array[i].eq(0) yield Settle() - startaddr //= 4 # instructions are 32-bit + startaddr //= 4 # instructions are 32-bit if mem.width == 32: - mask = ((1<<32)-1) + mask = ((1 << 32)-1) for ins in instructions: if isinstance(ins, tuple): insn, code = ins @@ -56,13 +56,13 @@ def setup_i_memory(imem, startaddr, instructions): yield mem._array[startaddr].eq(insn) yield Settle() if insn != 0: - print ("instr: %06x 0x%x %s" % (4*startaddr, insn, code)) + print("instr: %06x 0x%x %s" % (4*startaddr, insn, code)) startaddr += 1 startaddr = startaddr & mask return # 64 bit - mask = ((1<<64)-1) + mask = ((1 << 64)-1) for ins in instructions: if isinstance(ins, tuple): insn, code = ins @@ -154,7 +154,7 @@ class TestRunner(FHDLTestCase): yield pc_i.eq(pc) yield issuer.pc_i.ok.eq(1) - print ("instructions", instructions) + print("instructions", instructions) index = sim.pc.CIA.value//4 while index < len(instructions): @@ -205,10 +205,10 @@ if __name__ == "__main__": suite = unittest.TestSuite() # suite.addTest(TestRunner(HelloTestCases.test_data)) # suite.addTest(TestRunner(DivTestCase.test_data)) - #suite.addTest(TestRunner(AttnTestCase.test_data)) + # suite.addTest(TestRunner(AttnTestCase.test_data)) suite.addTest(TestRunner(GeneralTestCases.test_data)) - #suite.addTest(TestRunner(LDSTTestCase().test_data)) - #suite.addTest(TestRunner(CRTestCase().test_data)) + # suite.addTest(TestRunner(LDSTTestCase().test_data)) + # suite.addTest(TestRunner(CRTestCase().test_data)) # suite.addTest(TestRunner(ShiftRotTestCase.test_data)) # suite.addTest(TestRunner(LogicalTestCase.test_data)) # suite.addTest(TestRunner(ALUTestCase.test_data))