From: Eddie Hung Date: Thu, 19 Sep 2019 19:14:33 +0000 (-0700) Subject: Add support for SB_MAC16 CD and H registers X-Git-Tag: working-ls180~1039^2~93 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2766465a2bf73fcd490a160a124b6167851f2d10;p=yosys.git Add support for SB_MAC16 CD and H registers --- diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 4132857d6..7592593a6 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -33,8 +33,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm) log("\n"); log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--")); log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--")); + log("ffCD: %s %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"), log_id(st.ffCDrstmux, "--")); log("mul: %s\n", log_id(st.mul, "--")); log("ffFJKG: %s n/a %s\n", log_id(st.ffFJKG, "--"), log_id(st.ffFJKGrstmux, "--")); + log("ffH: %s n/a %s\n", log_id(st.ffH, "--"), log_id(st.ffHrstmux, "--")); log("add: %s\n", log_id(st.add, "--")); log("mux: %s\n", log_id(st.mux, "--")); log("ffO: %s\n", log_id(st.ffO, "--")); @@ -93,6 +95,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setParam("\\A_REG", st.ffA ? State::S1 : State::S0); cell->setParam("\\B_REG", st.ffB ? State::S1 : State::S0); + cell->setParam("\\C_REG", st.ffCD ? State::S1 : State::S0); + cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0); cell->setPort("\\AHOLD", State::S0); cell->setPort("\\BHOLD", State::S0); @@ -116,9 +120,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (st.ffB) log(" ffB:%s", log_id(st.ffB)); + if (st.ffCD) + log(" ffCD:%s", log_id(st.ffCD)); + if (st.ffFJKG) log(" ffFJKG:%s", log_id(st.ffFJKG)); + if (st.ffH) + log(" ffH:%s", log_id(st.ffH)); + if (st.ffO) log(" ffO:%s", log_id(st.ffO)); @@ -196,13 +206,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Remaining Parameters - cell->setParam("\\C_REG", State::S0); - cell->setParam("\\D_REG", State::S0); - cell->setParam("\\TOP_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0); cell->setParam("\\BOT_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0); cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffFJKG ? State::S1 : State::S0); - cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0); + cell->setParam("\\PIPELINE_16x16_MULT_REG2", st.ffH ? State::S1 : State::S0); cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2)); cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1); diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 22267aea7..532995da7 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -7,10 +7,10 @@ state add mux state addAB muxAB state ffAcepol ffBcepol ffCDcepol ffOcepol -state ffArstpol ffBrstpol ffCDrstpol ffFJKGrstpol ffOrstpol +state ffArstpol ffBrstpol ffCDrstpol ffOrstpol state ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffCD ffCDcemux ffCDrstmux -state ffFJKG ffFJKGrstmux ffO ffOcemux ffOrstmux +state ffFJKG ffFJKGrstmux ffH ffHrstmux ffO ffOcemux ffOrstmux // subpattern state argQ argD @@ -105,20 +105,18 @@ code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock clock_pol } endcode -code argD ffFJKG ffFJKGrstmux ffFJKGrstpol sigH sigO clock clock_pol +code argD ffFJKG ffFJKGrstmux sigH sigO clock clock_pol if (nusers(sigH) == 2 && (mul->type != \SB_MAC16 || - (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool()))) { + (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) { argD = sigH; subpattern(out_dffe); if (dff) { ffFJKG = dff; clock = dffclock; clock_pol = dffclock_pol; - if (dffrstmux) { + if (dffrstmux) ffFJKGrstmux = dffrstmux; - ffFJKGrstpol = dffrstpol; - } // F/J/K/G do not have a CE-like (hold) input if (dffcemux) reject; @@ -132,13 +130,43 @@ code argD ffFJKG ffFJKGrstmux ffFJKGrstpol sigH sigO clock clock_pol if (ffArstmux) { if (port(ffArstmux, \S) != port(ffFJKGrstmux, \S)) reject; - if (ffArstpol != ffFJKGrstpol) + if (ffArstpol != dffrstpol) reject; } if (ffBrstmux) { if (port(ffBrstmux, \S) != port(ffFJKGrstmux, \S)) reject; - if (ffBrstpol != ffFJKGrstpol) + if (ffBrstpol != dffrstpol) + reject; + } + + sigH = dffQ; + } + } +endcode + +code argD ffH ffHrstmux sigH sigO clock clock_pol + if (nusers(sigH) == 2 && + (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) { + argD = sigH; + subpattern(out_dffe); + if (dff) { + ffH = dff; + clock = dffclock; + clock_pol = dffclock_pol; + if (dffrstmux) + ffHrstmux = dffrstmux; + // H does not have a CE-like (hold) input + if (dffcemux) + reject; + + // Reset signal of H (IRSTBOT) shared with B + if ((ffBrstmux != NULL) != (ffHrstmux != NULL)) + reject; + if (ffBrstmux) { + if (port(ffBrstmux, \S) != port(ffHrstmux, \S)) + reject; + if (ffBrstpol != dffrstpol) reject; } @@ -244,6 +272,31 @@ code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol c cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool(); } } +endcode + +code argQ ffCD ffCDcemux ffCDrstmux ffCDcepol ffCDrstpol sigCD clock clock_pol + if (!sigCD.empty() && + (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) { + argQ = sigCD; + subpattern(in_dffe); + if (dff) { + ffCD = dff; + clock = dffclock; + clock_pol = dffclock_pol; + if (dffrstmux) { + ffCDrstmux = dffrstmux; + ffCDrstpol = dffrstpol; + } + if (dffcemux) { + ffCDcemux = dffcemux; + ffCDcepol = dffcepol; + } + sigCD = dffD; + } + } +endcode + +code sigCD sigCD.extend_u0(32, cd_signed); endcode