From: lkcl <lkcl@web>
Date: Thu, 14 Jul 2022 11:59:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1196
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=276b93feaf581755573cf3459c1d80668f8b641d;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 5f530d118..20206093a 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -289,7 +289,13 @@ available for "Custom non-approved purposes" according to the Power
 ISA Spec,
 is under severe design pressure as it is insufficient to hold
 the full extent of the instruction additions required to create
-a Hybrid 3D CPU-VPU-GPU.
+a Hybrid 3D CPU-VPU-GPU.  Akthough the wording of the Power ISA
+Specification leaves open the *possibility* of not needing to
+propose ISA Extensions to the ISA WG, it is clear that EXT022
+is an inappropriate location for a large high-profile Extension
+intended for mass-volume product deployment. Every in-good-faith effort will
+therefore be made to work with the OPF ISA WG to
+submit SVP64 via the External RFC Process.
 
 **Whilst SVP64 is only 5 instructions
 the heavy focus on VSX for the past 12 years has left the SFFS Level