From: Rodrigo Alejandro Melo Date: Sun, 2 Feb 2020 01:48:03 +0000 (-0300) Subject: Removed a line jump into the CHANGELOG X-Git-Tag: working-ls180~803^2~7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2774aae0f2395e121457a666dc16bedb4c3bba06;p=yosys.git Removed a line jump into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo --- diff --git a/CHANGELOG b/CHANGELOG index 4abfeec06..a908096e3 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -53,13 +53,12 @@ Yosys 0.9 .. Yosys 0.9-dev - Added support for flip-flops with synchronous reset to synth_xilinx - Added support for flip-flops with reset and enable to synth_xilinx - Added "check -mapped" - - Added checking of SystemVerilog always block types (always_comb, - always_latch and always_ff) + - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) - Added "xilinx_dffopt" pass - Added "scratchpad" pass - Added "abc9 -dff" - Added "synth_xilinx -dff" - - Improved support of $readmem[hb] file inclusion which is now relative to the Verilog file + - Improved support of $readmem[hb] Memory Content File inclusion Yosys 0.8 .. Yosys 0.9 ----------------------