From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Jun 2019 05:35:22 +0000 (+0100)
Subject: add comment, link to bugreport
X-Git-Tag: ls180-24jan2020~974
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2789fb65d1d70e70d45c0e2506dfc18d13939bb1;p=ieee754fpu.git

add comment, link to bugreport
---

diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index 8d7489c7..94c8a785 100644
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -1,4 +1,8 @@
-# IEEE Floating Point Divider
+"""IEEE754 Floating Point pipelined Divider
+
+Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
+
+"""
 
 from nmigen import Module
 from nmigen.cli import main, verilog
@@ -33,7 +37,9 @@ class FPDivStages(FPState, SimpleHandshake):
         """ links module to inputs and outputs
         """
 
-        # chain DivStage0 and DivStage1
+        # TODO.  clearly, this would be a for-loop, here, creating
+        # a huge number of stages (if radix-2 is used).  interestingly
+        # the number of stages will be data-dependent.
         m0mod = FPDivStage0Mod(self.width, self.id_wid)
         m1mod = FPDivStage1Mod(self.width, self.id_wid)