From: Gabe Black <gabe.black@gmail.com>
Date: Sat, 5 Dec 2020 01:43:19 +0000 (-0800)
Subject: dev: Cache the cacheLineSize in the DMA read FIFO.
X-Git-Tag: develop-gem5-snapshot~323
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27a41d6ef6de9ebf6db6ce256690307afbf165fa;p=gem5.git

dev: Cache the cacheLineSize in the DMA read FIFO.

This is a minor simplification which decouples the FIFO from the system
object at run time, although it does need to read the cache line size
out at construction time.

Change-Id: I57d96a676b9604663b6c9ed7c662640f507c5305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38482
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 0597306f6..429773de4 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -53,7 +53,7 @@ DmaPort::DmaPort(ClockedObject *dev, System *s,
     : RequestPort(dev->name() + ".dma", dev),
       device(dev), sys(s), requestorId(s->getRequestorId(dev)),
       sendEvent([this]{ sendDma(); }, dev->name()),
-      defaultSid(sid), defaultSSid(ssid)
+      defaultSid(sid), defaultSSid(ssid), cacheLineSize(s->cacheLineSize())
 { }
 
 void
@@ -159,7 +159,7 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
 
     DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
             event ? event->scheduled() : -1);
-    for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
+    for (ChunkGenerator gen(addr, size, cacheLineSize);
          !gen.done(); gen.next()) {
 
         req = std::make_shared<Request>(
@@ -286,7 +286,7 @@ DmaReadFifo::DmaReadFifo(DmaPort &_port, size_t size,
                          Request::Flags flags)
     : maxReqSize(max_req_size), fifoSize(size),
       reqFlags(flags), port(_port), proxy(port, port.sys->cacheLineSize()),
-      buffer(size)
+      cacheLineSize(port.sys->cacheLineSize()), buffer(size)
 {
     freeRequests.resize(max_pending);
     for (auto &e : freeRequests)
@@ -392,8 +392,7 @@ void
 DmaReadFifo::resumeFillFunctional()
 {
     const size_t fifo_space = buffer.capacity() - buffer.size();
-    const size_t kvm_watermark = port.sys->cacheLineSize();
-    if (fifo_space >= kvm_watermark || buffer.capacity() < kvm_watermark) {
+    if (fifo_space >= cacheLineSize || buffer.capacity() < cacheLineSize) {
         const size_t block_remaining = endAddr - nextAddr;
         const size_t xfer_size = std::min(fifo_space, block_remaining);
         std::vector<uint8_t> tmp_buffer(xfer_size);
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 4dec839f9..f61722394 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -137,6 +137,8 @@ class DmaPort : public RequestPort, public Drainable
     /** Default substreamId */
     const uint32_t defaultSSid;
 
+    const int cacheLineSize;
+
   protected:
 
     bool recvTimingResp(PacketPtr pkt) override;
@@ -474,6 +476,8 @@ class DmaReadFifo : public Drainable, public Serializable
     DmaPort &port;
     PortProxy proxy;
 
+    const int cacheLineSize;
+
   private:
     class DmaDoneEvent : public Event
     {