From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Dec 2021 13:32:16 +0000 (+0000)
Subject: add in I-Cache into LoadStore1 - presently unused - so as to start on
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27a4f0b59f5332b52b10273b1cf42f56ffcbe784;p=soc.git

add in I-Cache into LoadStore1 - presently unused - so as to start on
a unit test (test_loadstore1.py).  this is not a normal place to start,
but I-Cache links cross-wise into so many other dependent areas that
it is quite tricky
---

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index c43dce18..0b539343 100644
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -39,12 +39,15 @@ def setup_mmu():
     m.submodules.ldst = ldst = cmpi.pi
     m.submodules.mmu = mmu = MMU()
     dcache = ldst.dcache
+    icache = ldst.icache
 
     l_in, l_out = mmu.l_in, mmu.l_out
     d_in, d_out = dcache.d_in, dcache.d_out
+    i_in, i_out = icache.i_in, icache.i_out
 
-    # link mmu and dcache together
+    # link mmu, dcache and icache together
     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
+    m.d.comb += icache.m_in.eq(mmu.i_out) # MMUToICacheType
     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 
     # link ldst and MMU together
diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index b7d03b04..fdf18292 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -25,6 +25,7 @@ from nmutil.util import rising_edge, Display
 from enum import Enum, unique
 
 from soc.experiment.dcache import DCache
+from soc.experiment.icache import ICache
 from soc.experiment.pimem import PortInterfaceBase
 from soc.experiment.mem_types import LoadStore1ToMMUType
 from soc.experiment.mem_types import MMUToLoadStore1Type
@@ -58,6 +59,7 @@ class LDSTRequest(RecordObject):
         self.priv_mode     = Signal()
         self.align_intr    = Signal()
 
+
 # glue logic for microwatt mmu and dcache
 class LoadStore1(PortInterfaceBase):
     def __init__(self, pspec):
@@ -69,15 +71,19 @@ class LoadStore1(PortInterfaceBase):
 
         super().__init__(regwid, addrwid)
         self.dcache = DCache()
+        self.icache = ICache()
         # these names are from the perspective of here (LoadStore1)
         self.d_out  = self.dcache.d_in     # in to dcache is out for LoadStore
         self.d_in = self.dcache.d_out      # out from dcache is in for LoadStore
+        self.i_out  = self.icache.i_in     # in to icache is out for LoadStore
+        self.i_in = self.icache.i_out      # out from icache is in for LoadStore
         self.m_out  = LoadStore1ToMMUType() # out *to* MMU
         self.m_in = MMUToLoadStore1Type()   # in *from* MMU
         self.req = LDSTRequest(name="ldst_req")
 
         # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
         self.dbus = Record(make_wb_layout(pspec))
+        self.ibus = Record(make_wb_layout(pspec))
 
         # for creating a single clock blip to DCache
         self.d_valid = Signal()
@@ -180,11 +186,13 @@ class LoadStore1(PortInterfaceBase):
         sync += self.done_delay.eq(self.done)
         sync += self.load_data_delay.eq(self.load_data)
 
-        # create dcache module
+        # create dcache and icache module
         m.submodules.dcache = dcache = self.dcache
+        m.submodules.icache = icache = self.icache
 
         # temp vars
         d_out, d_in, dbus = self.d_out, self.d_in, self.dbus
+        i_out, i_in, ibus = self.i_out, self.i_in, self.ibus
         m_out, m_in = self.m_out, self.m_in
         exc = self.pi.exc_o
         exception = exc.happened