From: Eric Anholt <eric@anholt.net>
Date: Wed, 11 May 2011 19:43:28 +0000 (-0700)
Subject: i965/fs: Fix discard and alpha test in 16-wide.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27b03926618ddcafabb7b61e652fe6458b017b24;p=mesa.git

i965/fs: Fix discard and alpha test in 16-wide.

As of gen6, alt-mode (which we use) MOVs of floats are not raw --
they'll modify infs/nans.  This broke discard and alpha test in
16-wide, where apparently the upper 8 bits of the pixel enables being
set were causing the whole value to get trashed upon being moved.
Treating the values as UD instead of float makes sure they get
preserved.  While I'm here, replace the two 8-wide moves of the halves
of the header with a single compressed move.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36648
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index bd5e8d2e843..018a16e4322 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2317,9 +2317,11 @@ fs_visitor::generate_fb_write(fs_inst *inst)
 
    if (inst->header_present) {
       if (intel->gen >= 6) {
+	 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
 	 brw_MOV(p,
-		 brw_message_reg(inst->base_mrf),
-		 brw_vec8_grf(0, 0));
+		 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
+		 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+	 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 
 	 if (inst->target > 0) {
 	    /* Set the render target index for choosing BLEND_STATE. */
@@ -2337,11 +2339,11 @@ fs_visitor::generate_fb_write(fs_inst *inst)
 	 implied_header = brw_null_reg();
       } else {
 	 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
-      }
 
-      brw_MOV(p,
-	      brw_message_reg(inst->base_mrf + 1),
-	      brw_vec8_grf(1, 0));
+	 brw_MOV(p,
+		 brw_message_reg(inst->base_mrf + 1),
+		 brw_vec8_grf(1, 0));
+      }
    } else {
       implied_header = brw_null_reg();
    }