From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 6 Dec 2017 21:22:05 +0000 (+0100)
Subject: targets/sim: fix
X-Git-Tag: 24jan2021_ls180~1791
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27d37fa95d201e90b130825aeaebcecc607806fe;p=litex.git

targets/sim: fix
---

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 04371fd9..a10479d2 100755
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -23,6 +23,11 @@ from liteeth.core.mac import LiteEthMAC
 from litex.build.sim.config import SimConfig
 
 class BaseSoC(SoCSDRAM):
+    interrupt_map = {
+        "uart": 2,
+    }
+    interrupt_map.update(SoCSDRAM.interrupt_map)
+
     def __init__(self, **kwargs):
         platform = sim.Platform()
         SoCSDRAM.__init__(self, platform,