From: whitequark <whitequark@whitequark.org>
Date: Thu, 13 Dec 2018 04:34:22 +0000 (+0000)
Subject: back.rtlil: fix swapped operands in sync assign.
X-Git-Tag: working~317
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27d3dfc45374d6e157ef4fa7ee5821fa9011e77c;p=nmigen.git

back.rtlil: fix swapped operands in sync assign.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 490e3e7..0e06d20 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -495,9 +495,9 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
                 for trigger in triggers:
                     with process.sync(*trigger) as sync:
                         for signal in signals:
-                            rhs_sigspec = xformer(signal)
+                            lhs_sigspec = xformer(signal)
                             with xformer.lhs():
-                                sync.update(xformer(signal), rhs_sigspec)
+                                sync.update(lhs_sigspec, xformer(signal))
 
     # Finally, collect the names we've given to our ports in RTLIL, and correlate these with
     # the signals represented by these ports. If we are a submodule, this will be necessary