From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 15 Aug 2019 19:19:34 +0000 (-0700)
Subject: ffH -> ffFJKG
X-Git-Tag: working-ls180~1039^2~236
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27d5df9467fb425234a466d0d63b8a94e37ca596;p=yosys.git

ffH -> ffFJKG
---

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 6f0539679..a1a397b83 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -38,7 +38,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log("ffA:    %s\n", log_id(st.ffA, "--"));
 	log("ffB:    %s\n", log_id(st.ffB, "--"));
 	log("mul:    %s\n", log_id(st.mul, "--"));
-	log("ffH:    %s\n", log_id(st.ffH, "--"));
+	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
 	log("addAB:  %s\n", log_id(st.addAB, "--"));
 	log("muxAB:  %s\n", log_id(st.muxAB, "--"));
 	log("ffO_lo: %s\n", log_id(st.ffO_lo, "--"));
@@ -119,8 +119,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		if (st.ffB)
 			log(" ffB:%s", log_id(st.ffB));
 
-		if (st.ffH)
-			log(" ffH:%s", log_id(st.ffH));
+		if (st.ffFJKG)
+			log(" ffFJKG:%s", log_id(st.ffFJKG));
 
 		if (st.ffO_lo)
 			log(" ffO_lo:%s", log_id(st.ffO_lo));
@@ -206,9 +206,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\C_REG", State::S0);
 	cell->setParam("\\D_REG", State::S0);
 
-	cell->setParam("\\TOP_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
-	cell->setParam("\\BOT_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0);
+	cell->setParam("\\TOP_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
+	cell->setParam("\\BOT_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
+	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffFJKG ? State::S1 : State::S0);
 	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
 	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO_hi ? 1 : (st.addAB ? 0 : 3), 2));
@@ -229,7 +229,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		pm.autoremove(st.mul);
 	else
 		pm.blacklist(st.mul);
-	pm.autoremove(st.ffH);
+	pm.autoremove(st.ffFJKG);
 	pm.autoremove(st.addAB);
 	if (st.ffO_lo) {
 			SigSpec O = st.sigO.extract(0,std::min(16,st.ffO_lo->getParam("\\WIDTH").as_int()));
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index d64c8a391..11064e072 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -82,11 +82,11 @@ code sigB clock clock_pol
 	}
 endcode
 
-match ffH
+match ffFJKG
 	if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
-	select ffH->type.in($dff)
-	select nusers(port(ffH, \D)) == 2
-	index <SigSpec> port(ffH, \D) === sigH
+	select ffFJKG->type.in($dff)
+	select nusers(port(ffFJKG, \D)) == 2
+	index <SigSpec> port(ffFJKG, \D) === sigH
 	// Ensure pipeline register is not already used
 	optional
 endmatch
@@ -94,16 +94,16 @@ endmatch
 code sigH sigO clock clock_pol
 	sigO = sigH;
 
-	if (ffH) {
-		sigH = port(ffH, \Q);
+	if (ffFJKG) {
+		sigH = port(ffFJKG, \Q);
 		for (auto b : sigH)
 			if (b.wire->get_bool_attribute(\keep))
 				reject;
 
 		sigO = sigH;
 
-		SigBit c = port(ffH, \CLK).as_bit();
-		bool cp = param(ffH, \CLK_POLARITY).as_bool();
+		SigBit c = port(ffFJKG, \CLK).as_bit();
+		bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
 
 		if (clock != SigBit() && (c != clock || cp != clock_pol))
 			reject;