From: Eric Anholt Date: Thu, 20 Jun 2013 18:53:27 +0000 (-0700) Subject: i915: Remove separate stencil code. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=27eedca;p=mesa.git i915: Remove separate stencil code. This was formerly-shared code for supporting gen5+. Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c index d3864465b26..22d0feaacf8 100644 --- a/src/mesa/drivers/dri/i915/i915_context.c +++ b/src/mesa/drivers/dri/i915/i915_context.c @@ -115,7 +115,6 @@ intel_init_texture_formats(struct gl_context *ctx) /* Depth and stencil */ ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true; ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true; - ctx->TextureFormatSupported[MESA_FORMAT_S8] = intel->has_separate_stencil; /* * This was disabled in initial FBO enabling to avoid combinations diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c index 827d6c69b97..19d5436bc8b 100644 --- a/src/mesa/drivers/dri/i915/intel_context.c +++ b/src/mesa/drivers/dri/i915/intel_context.c @@ -499,8 +499,6 @@ intelInitContext(struct intel_context *intel, intel->needs_ff_sync = true; } - intel->has_separate_stencil = intel->intelScreen->hw_has_separate_stencil; - intel->must_use_separate_stencil = intel->intelScreen->hw_must_use_separate_stencil; intel->has_llc = intel->intelScreen->hw_has_llc; intel->has_swizzling = intel->intelScreen->hw_has_swizzling; diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index c7449f44087..1c8c87ddb33 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -221,8 +221,6 @@ struct intel_context bool is_baytrail; bool is_g4x; bool is_945; - bool has_separate_stencil; - bool must_use_separate_stencil; bool has_llc; bool has_swizzling; diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c b/src/mesa/drivers/dri/i915/intel_fbo.c index 83699c0549e..52beaf2c16c 100644 --- a/src/mesa/drivers/dri/i915/intel_fbo.c +++ b/src/mesa/drivers/dri/i915/intel_fbo.c @@ -58,12 +58,9 @@ struct intel_region* intel_get_rb_region(struct gl_framebuffer *fb, GLuint attIndex) { struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, attIndex); - if (irb && irb->mt) { - if (attIndex == BUFFER_STENCIL && irb->mt->stencil_mt) - return irb->mt->stencil_mt->region; - else - return irb->mt->region; - } else + if (irb && irb->mt) + return irb->mt->region; + else return NULL; } @@ -197,12 +194,7 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer case GL_STENCIL_INDEX8_EXT: case GL_STENCIL_INDEX16_EXT: /* These aren't actual texture formats, so force them here. */ - if (intel->has_separate_stencil) { - rb->Format = MESA_FORMAT_S8; - } else { - assert(!intel->must_use_separate_stencil); - rb->Format = MESA_FORMAT_S8_Z24; - } + rb->Format = MESA_FORMAT_S8_Z24; break; } @@ -561,18 +553,15 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) if (depthRb) depth_mt = depthRb->mt; - if (stencilRb) { + if (stencilRb) stencil_mt = stencilRb->mt; - if (stencil_mt->stencil_mt) - stencil_mt = stencil_mt->stencil_mt; - } if (depth_mt && stencil_mt) { + /* Make sure that the depth and stencil buffers are actually the same + * slice of the same miptree, since we only support packed + * depth/stencil. + */ if (depth_mt == stencil_mt) { - /* For true packed depth/stencil (not faked on prefers-separate-stencil - * hardware) we need to be sure they're the same level/layer, since - * we'll be emitting a single packet describing the packed setup. - */ if (depthRb->mt_level != stencilRb->mt_level || depthRb->mt_layer != stencilRb->mt_layer) { fbo_incomplete(fb, @@ -584,15 +573,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) stencilRb->mt_layer); } } else { - if (!intel->has_separate_stencil) { - fbo_incomplete(fb, "FBO incomplete: separate stencil " - "unsupported\n"); - } - if (stencil_mt->format != MESA_FORMAT_S8) { - fbo_incomplete(fb, "FBO incomplete: separate stencil is %s " - "instead of S8\n", - _mesa_get_format_name(stencil_mt->format)); - } + fbo_incomplete(fb, "FBO incomplete: separate stencil unsupported\n"); } } diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c index 8b2b3fe0578..42bfee922da 100644 --- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c @@ -114,38 +114,6 @@ intel_miptree_create_layout(struct intel_context *intel, mt->physical_height0 = height0; mt->physical_depth0 = depth0; - if (!for_bo && - _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL && - (intel->must_use_separate_stencil)) { - mt->stencil_mt = intel_miptree_create(intel, - mt->target, - MESA_FORMAT_S8, - mt->first_level, - mt->last_level, - mt->logical_width0, - mt->logical_height0, - mt->logical_depth0, - true, - INTEL_MIPTREE_TILING_ANY); - if (!mt->stencil_mt) { - intel_miptree_release(&mt); - return NULL; - } - - /* Fix up the Z miptree format for how we're splitting out separate - * stencil. Gen7 expects there to be no stencil bits in its depth buffer. - */ - if (mt->format == MESA_FORMAT_S8_Z24) { - mt->format = MESA_FORMAT_X8_Z24; - } else if (mt->format == MESA_FORMAT_Z32_FLOAT_X24S8) { - mt->format = MESA_FORMAT_Z32_FLOAT; - mt->cpp = 4; - } else { - _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n", - _mesa_get_format_name(mt->format)); - } - } - intel_get_texture_alignment_unit(intel, mt->format, &mt->align_w, &mt->align_h); @@ -168,14 +136,6 @@ intel_miptree_choose_tiling(struct intel_context *intel, enum intel_miptree_tiling_mode requested, struct intel_mipmap_tree *mt) { - - if (format == MESA_FORMAT_S8) { - /* The stencil buffer is W tiled. However, we request from the kernel a - * non-tiled buffer because the GTT is incapable of W fencing. - */ - return I915_TILING_NONE; - } - /* Some usages may want only one type of tiling, like depth miptrees (Y * tiled), or temporary BOs for uploading data once (linear). */ @@ -282,12 +242,6 @@ intel_miptree_create(struct intel_context *intel, total_width = mt->total_width; total_height = mt->total_height; - if (format == MESA_FORMAT_S8) { - /* Align to size of W tile, 64x64. */ - total_width = ALIGN(total_width, 64); - total_height = ALIGN(total_height, 64); - } - uint32_t tiling = intel_miptree_choose_tiling(intel, format, width0, requested_tiling, mt); @@ -461,7 +415,6 @@ intel_miptree_release(struct intel_mipmap_tree **mt) DBG("%s deleting %p\n", __FUNCTION__, *mt); intel_region_release(&((*mt)->region)); - intel_miptree_release(&(*mt)->stencil_mt); for (i = 0; i < MAX_TEXTURE_LEVELS; i++) { free((*mt)->level[i].slice); @@ -511,10 +464,6 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt, assert(target_to_target(image->TexObject->Target) == mt->target); gl_format mt_format = mt->format; - if (mt->format == MESA_FORMAT_X8_Z24 && mt->stencil_mt) - mt_format = MESA_FORMAT_S8_Z24; - if (mt->format == MESA_FORMAT_Z32_FLOAT && mt->stencil_mt) - mt_format = MESA_FORMAT_Z32_FLOAT_X24S8; if (mt->etc_format != MESA_FORMAT_NONE) mt_format = mt->etc_format; @@ -686,17 +635,6 @@ intel_miptree_copy_slice_sw(struct intel_context *intel, intel_miptree_unmap(intel, dst_mt, level, slice); intel_miptree_unmap(intel, src_mt, level, slice); - - /* Don't forget to copy the stencil data over, too. We could have skipped - * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map - * shuffling the two data sources in/out of temporary storage instead of - * the direct mapping we get this way. - */ - if (dst_mt->stencil_mt) { - assert(src_mt->stencil_mt); - intel_miptree_copy_slice_sw(intel, dst_mt->stencil_mt, src_mt->stencil_mt, - level, slice, width, height); - } } static void @@ -726,18 +664,6 @@ intel_miptree_copy_slice(struct intel_context *intel, width = ALIGN(width, dst_mt->align_w); } - /* If it's a packed depth/stencil buffer with separate stencil, the blit - * below won't apply since we can't do the depth's Y tiling or the - * stencil's W tiling in the blitter. - */ - if (src_mt->stencil_mt) { - intel_miptree_copy_slice_sw(intel, - dst_mt, src_mt, - level, slice, - width, height); - return; - } - uint32_t dst_x, dst_y, src_x, src_y; intel_miptree_get_image_offset(dst_mt, level, slice, &dst_x, &dst_y); intel_miptree_get_image_offset(src_mt, level, slice, &src_x, &src_y); @@ -792,62 +718,6 @@ intel_miptree_copy_teximage(struct intel_context *intel, intel_obj->needs_validate = true; } -/** - * \brief Get pointer offset into stencil buffer. - * - * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we - * must decode the tile's layout in software. - * - * See - * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile - * Format. - * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm - * - * Even though the returned offset is always positive, the return type is - * signed due to - * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137 - * mesa: Fix return type of _mesa_get_format_bytes() (#37351) - */ -static intptr_t -intel_offset_S8(uint32_t stride, uint32_t x, uint32_t y, bool swizzled) -{ - uint32_t tile_size = 4096; - uint32_t tile_width = 64; - uint32_t tile_height = 64; - uint32_t row_size = 64 * stride; - - uint32_t tile_x = x / tile_width; - uint32_t tile_y = y / tile_height; - - /* The byte's address relative to the tile's base addres. */ - uint32_t byte_x = x % tile_width; - uint32_t byte_y = y % tile_height; - - uintptr_t u = tile_y * row_size - + tile_x * tile_size - + 512 * (byte_x / 8) - + 64 * (byte_y / 8) - + 32 * ((byte_y / 4) % 2) - + 16 * ((byte_x / 4) % 2) - + 8 * ((byte_y / 2) % 2) - + 4 * ((byte_x / 2) % 2) - + 2 * (byte_y % 2) - + 1 * (byte_x % 2); - - if (swizzled) { - /* adjust for bit6 swizzling */ - if (((byte_x / 8) % 2) == 1) { - if (((byte_y / 8) % 2) == 0) { - u += 64; - } else { - u -= 64; - } - } - } - - return u; -} - void * intel_miptree_map_raw(struct intel_context *intel, struct intel_mipmap_tree *mt) { @@ -995,81 +865,6 @@ intel_miptree_unmap_blit(struct intel_context *intel, intel_miptree_release(&map->mt); } -static void -intel_miptree_map_s8(struct intel_context *intel, - struct intel_mipmap_tree *mt, - struct intel_miptree_map *map, - unsigned int level, unsigned int slice) -{ - map->stride = map->w; - map->buffer = map->ptr = malloc(map->stride * map->h); - if (!map->buffer) - return; - - /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no - * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless - * invalidate is set, since we'll be writing the whole rectangle from our - * temporary buffer back out. - */ - if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) { - uint8_t *untiled_s8_map = map->ptr; - uint8_t *tiled_s8_map = intel_miptree_map_raw(intel, mt); - unsigned int image_x, image_y; - - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); - - for (uint32_t y = 0; y < map->h; y++) { - for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t offset = intel_offset_S8(mt->region->pitch, - x + image_x + map->x, - y + image_y + map->y, - intel->has_swizzling); - untiled_s8_map[y * map->w + x] = tiled_s8_map[offset]; - } - } - - intel_miptree_unmap_raw(intel, mt); - - DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__, - map->x, map->y, map->w, map->h, - mt, map->x + image_x, map->y + image_y, map->ptr, map->stride); - } else { - DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__, - map->x, map->y, map->w, map->h, - mt, map->ptr, map->stride); - } -} - -static void -intel_miptree_unmap_s8(struct intel_context *intel, - struct intel_mipmap_tree *mt, - struct intel_miptree_map *map, - unsigned int level, - unsigned int slice) -{ - if (map->mode & GL_MAP_WRITE_BIT) { - unsigned int image_x, image_y; - uint8_t *untiled_s8_map = map->ptr; - uint8_t *tiled_s8_map = intel_miptree_map_raw(intel, mt); - - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); - - for (uint32_t y = 0; y < map->h; y++) { - for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t offset = intel_offset_S8(mt->region->pitch, - x + map->x, - y + map->y, - intel->has_swizzling); - tiled_s8_map[offset] = untiled_s8_map[y * map->w + x]; - } - } - - intel_miptree_unmap_raw(intel, mt); - } - - free(map->buffer); -} - static void intel_miptree_map_etc(struct intel_context *intel, struct intel_mipmap_tree *mt, @@ -1122,147 +917,6 @@ intel_miptree_unmap_etc(struct intel_context *intel, free(map->buffer); } -/** - * Mapping function for packed depth/stencil miptrees backed by real separate - * miptrees for depth and stencil. - * - * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer - * separate from the depth buffer. Yet at the GL API level, we have to expose - * packed depth/stencil textures and FBO attachments, and Mesa core expects to - * be able to map that memory for texture storage and glReadPixels-type - * operations. We give Mesa core that access by mallocing a temporary and - * copying the data between the actual backing store and the temporary. - */ -static void -intel_miptree_map_depthstencil(struct intel_context *intel, - struct intel_mipmap_tree *mt, - struct intel_miptree_map *map, - unsigned int level, unsigned int slice) -{ - struct intel_mipmap_tree *z_mt = mt; - struct intel_mipmap_tree *s_mt = mt->stencil_mt; - bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT; - int packed_bpp = map_z32f_x24s8 ? 8 : 4; - - map->stride = map->w * packed_bpp; - map->buffer = map->ptr = malloc(map->stride * map->h); - if (!map->buffer) - return; - - /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no - * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless - * invalidate is set, since we'll be writing the whole rectangle from our - * temporary buffer back out. - */ - if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) { - uint32_t *packed_map = map->ptr; - uint8_t *s_map = intel_miptree_map_raw(intel, s_mt); - uint32_t *z_map = intel_miptree_map_raw(intel, z_mt); - unsigned int s_image_x, s_image_y; - unsigned int z_image_x, z_image_y; - - intel_miptree_get_image_offset(s_mt, level, slice, - &s_image_x, &s_image_y); - intel_miptree_get_image_offset(z_mt, level, slice, - &z_image_x, &z_image_y); - - for (uint32_t y = 0; y < map->h; y++) { - for (uint32_t x = 0; x < map->w; x++) { - int map_x = map->x + x, map_y = map->y + y; - ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch, - map_x + s_image_x, - map_y + s_image_y, - intel->has_swizzling); - ptrdiff_t z_offset = ((map_y + z_image_y) * - (z_mt->region->pitch / 4) + - (map_x + z_image_x)); - uint8_t s = s_map[s_offset]; - uint32_t z = z_map[z_offset]; - - if (map_z32f_x24s8) { - packed_map[(y * map->w + x) * 2 + 0] = z; - packed_map[(y * map->w + x) * 2 + 1] = s; - } else { - packed_map[y * map->w + x] = (s << 24) | (z & 0x00ffffff); - } - } - } - - intel_miptree_unmap_raw(intel, s_mt); - intel_miptree_unmap_raw(intel, z_mt); - - DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n", - __FUNCTION__, - map->x, map->y, map->w, map->h, - z_mt, map->x + z_image_x, map->y + z_image_y, - s_mt, map->x + s_image_x, map->y + s_image_y, - map->ptr, map->stride); - } else { - DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__, - map->x, map->y, map->w, map->h, - mt, map->ptr, map->stride); - } -} - -static void -intel_miptree_unmap_depthstencil(struct intel_context *intel, - struct intel_mipmap_tree *mt, - struct intel_miptree_map *map, - unsigned int level, - unsigned int slice) -{ - struct intel_mipmap_tree *z_mt = mt; - struct intel_mipmap_tree *s_mt = mt->stencil_mt; - bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT; - - if (map->mode & GL_MAP_WRITE_BIT) { - uint32_t *packed_map = map->ptr; - uint8_t *s_map = intel_miptree_map_raw(intel, s_mt); - uint32_t *z_map = intel_miptree_map_raw(intel, z_mt); - unsigned int s_image_x, s_image_y; - unsigned int z_image_x, z_image_y; - - intel_miptree_get_image_offset(s_mt, level, slice, - &s_image_x, &s_image_y); - intel_miptree_get_image_offset(z_mt, level, slice, - &z_image_x, &z_image_y); - - for (uint32_t y = 0; y < map->h; y++) { - for (uint32_t x = 0; x < map->w; x++) { - ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch, - x + s_image_x + map->x, - y + s_image_y + map->y, - intel->has_swizzling); - ptrdiff_t z_offset = ((y + z_image_y) * - (z_mt->region->pitch / 4) + - (x + z_image_x)); - - if (map_z32f_x24s8) { - z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0]; - s_map[s_offset] = packed_map[(y * map->w + x) * 2 + 1]; - } else { - uint32_t packed = packed_map[y * map->w + x]; - s_map[s_offset] = packed >> 24; - z_map[z_offset] = packed; - } - } - } - - intel_miptree_unmap_raw(intel, s_mt); - intel_miptree_unmap_raw(intel, z_mt); - - DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n", - __FUNCTION__, - map->x, map->y, map->w, map->h, - z_mt, _mesa_get_format_name(z_mt->format), - map->x + z_image_x, map->y + z_image_y, - s_mt, map->x + s_image_x, map->y + s_image_y, - map->ptr, map->stride); - } - - free(map->buffer); -} - /** * Create and attach a map to the miptree at (level, slice). Return the * attached map. @@ -1331,13 +985,9 @@ intel_miptree_map(struct intel_context *intel, return; } - if (mt->format == MESA_FORMAT_S8) { - intel_miptree_map_s8(intel, mt, map, level, slice); - } else if (mt->etc_format != MESA_FORMAT_NONE && - !(mode & BRW_MAP_DIRECT_BIT)) { + if (mt->etc_format != MESA_FORMAT_NONE && + !(mode & BRW_MAP_DIRECT_BIT)) { intel_miptree_map_etc(intel, mt, map, level, slice); - } else if (mt->stencil_mt && !(mode & BRW_MAP_DIRECT_BIT)) { - intel_miptree_map_depthstencil(intel, mt, map, level, slice); } /* See intel_miptree_blit() for details on the 32k pitch limit. */ else if (intel->has_llc && @@ -1376,13 +1026,9 @@ intel_miptree_unmap(struct intel_context *intel, DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__, mt, _mesa_get_format_name(mt->format), level, slice); - if (mt->format == MESA_FORMAT_S8) { - intel_miptree_unmap_s8(intel, mt, map, level, slice); - } else if (mt->etc_format != MESA_FORMAT_NONE && - !(map->mode & BRW_MAP_DIRECT_BIT)) { + if (mt->etc_format != MESA_FORMAT_NONE && + !(map->mode & BRW_MAP_DIRECT_BIT)) { intel_miptree_unmap_etc(intel, mt, map, level, slice); - } else if (mt->stencil_mt && !(map->mode & BRW_MAP_DIRECT_BIT)) { - intel_miptree_unmap_depthstencil(intel, mt, map, level, slice); } else if (map->mt) { intel_miptree_unmap_blit(intel, mt, map, level, slice); } else { diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h index 55dd7b5a480..e4cb6264bbb 100644 --- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h @@ -158,13 +158,6 @@ struct intel_mipmap_tree * Generally, this is just the same as the gl_texture_image->TexFormat or * gl_renderbuffer->Format. * - * However, for textures and renderbuffers with packed depth/stencil formats - * on hardware where we want or need to use separate stencil, there will be - * two miptrees for storing the data. If the depthstencil texture or rb is - * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be - * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be - * MESA_FORMAT_X8_Z24. - * * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc. */ @@ -232,18 +225,6 @@ struct intel_mipmap_tree */ uint32_t offset; - /** - * \brief Stencil miptree for depthstencil textures. - * - * This miptree is used for depthstencil textures and renderbuffers that - * require separate stencil. It always has the true copy of the stencil - * bits, regardless of mt->format. - * - * \see intel_miptree_map_depthstencil() - * \see intel_miptree_unmap_depthstencil() - */ - struct intel_mipmap_tree *stencil_mt; - /* These are also refcounted: */ GLuint refcount; @@ -361,30 +342,6 @@ intel_miptree_copy_teximage(struct intel_context *intel, struct intel_texture_image *intelImage, struct intel_mipmap_tree *dst_mt, bool invalidate); -/** - * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for - * the given miptree slice. - * - * \see intel_mipmap_tree::stencil_mt - */ -void -intel_miptree_s8z24_scatter(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t slice); - -/** - * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the - * given miptree slice. - * - * \see intel_mipmap_tree::stencil_mt - */ -void -intel_miptree_s8z24_gather(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer); - /**\}*/ /* i915_mipmap_tree.c: diff --git a/src/mesa/drivers/dri/i915/intel_regions.h b/src/mesa/drivers/dri/i915/intel_regions.h index 1fb6b275772..5c612a925b9 100644 --- a/src/mesa/drivers/dri/i915/intel_regions.h +++ b/src/mesa/drivers/dri/i915/intel_regions.h @@ -149,7 +149,6 @@ struct __DRIimageRec { GLuint height; GLuint tile_x; GLuint tile_y; - bool has_depthstencil; void *data; }; diff --git a/src/mesa/drivers/dri/i915/intel_screen.c b/src/mesa/drivers/dri/i915/intel_screen.c index 4a7d1cadc1d..180daee00da 100644 --- a/src/mesa/drivers/dri/i915/intel_screen.c +++ b/src/mesa/drivers/dri/i915/intel_screen.c @@ -316,7 +316,6 @@ intel_setup_image_from_dimensions(__DRIimage *image) image->height = image->region->height; image->tile_x = 0; image->tile_y = 0; - image->has_depthstencil = false; } static inline uint32_t @@ -398,7 +397,6 @@ intel_create_image_from_renderbuffer(__DRIcontext *context, intel_region_reference(&image->region, irb->mt->region); intel_setup_image_from_dimensions(image); image->dri_format = intel_dri_format(image->format); - image->has_depthstencil = irb->mt->stencil_mt? true : false; rb->NeedsFinishRenderTexture = true; return image; @@ -453,7 +451,6 @@ intel_create_image_from_texture(__DRIcontext *context, int target, image->data = loaderPrivate; intel_setup_image_from_mipmap_tree(intel, image, iobj->mt, level, zoffset); image->dri_format = intel_dri_format(image->format); - image->has_depthstencil = iobj->mt->stencil_mt? true : false; if (image->dri_format == MESA_FORMAT_NONE) { *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; free(image); @@ -565,7 +562,6 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) image->height = orig_image->height; image->tile_x = orig_image->tile_x; image->tile_y = orig_image->tile_y; - image->has_depthstencil = orig_image->has_depthstencil; image->data = loaderPrivate; memcpy(image->strides, orig_image->strides, sizeof(image->strides)); @@ -849,20 +845,13 @@ intelCreateBuffer(__DRIscreen * driScrnPriv, if (mesaVis->depthBits == 24) { assert(mesaVis->stencilBits == 8); - if (screen->hw_has_separate_stencil) { - rb = intel_create_private_renderbuffer(MESA_FORMAT_X8_Z24); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); - rb = intel_create_private_renderbuffer(MESA_FORMAT_S8); - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base); - } else { - /* - * Use combined depth/stencil. Note that the renderbuffer is - * attached to two attachment points. - */ - rb = intel_create_private_renderbuffer(MESA_FORMAT_S8_Z24); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base); - } + /* + * Use combined depth/stencil. Note that the renderbuffer is + * attached to two attachment points. + */ + rb = intel_create_private_renderbuffer(MESA_FORMAT_S8_Z24); + _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); + _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base); } else if (mesaVis->depthBits == 16) { assert(mesaVis->stencilBits == 0); @@ -976,31 +965,6 @@ intel_init_bufmgr(struct intel_screen *intelScreen) return true; } -/** - * Override intel_screen.hw_has_separate_stencil with environment variable - * INTEL_SEPARATE_STENCIL. - * - * Valid values for INTEL_SEPARATE_STENCIL are "0" and "1". If an invalid - * valid value is encountered, a warning is emitted and INTEL_SEPARATE_STENCIL - * is ignored. - */ -static void -intel_override_separate_stencil(struct intel_screen *screen) -{ - const char *s = getenv("INTEL_SEPARATE_STENCIL"); - if (!s) { - return; - } else if (!strncmp("0", s, 2)) { - screen->hw_has_separate_stencil = false; - } else if (!strncmp("1", s, 2)) { - screen->hw_has_separate_stencil = true; - } else { - fprintf(stderr, - "warning: env variable INTEL_SEPARATE_STENCIL=\"%s\" has " - "invalid value and is ignored", s); - } -} - static bool intel_detect_swizzling(struct intel_screen *screen) { @@ -1222,9 +1186,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) intelScreen->gen = 2; } - intelScreen->hw_has_separate_stencil = intelScreen->gen >= 6; - intelScreen->hw_must_use_separate_stencil = intelScreen->gen >= 7; - int has_llc = 0; bool success = intel_get_param(intelScreen->driScrnPriv, I915_PARAM_HAS_LLC, &has_llc); @@ -1233,8 +1194,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) else if (!success && intelScreen->gen >= 6) intelScreen->hw_has_llc = true; - intel_override_separate_stencil(intelScreen); - intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen); set_max_gl_versions(intelScreen); diff --git a/src/mesa/drivers/dri/i915/intel_screen.h b/src/mesa/drivers/dri/i915/intel_screen.h index 188e2c09c99..4ce8a071b77 100644 --- a/src/mesa/drivers/dri/i915/intel_screen.h +++ b/src/mesa/drivers/dri/i915/intel_screen.h @@ -49,14 +49,6 @@ struct intel_screen bool no_hw; - /* - * The hardware hiz and separate stencil fields are needed in intel_screen, - * rather than solely in intel_context, because glXCreatePbuffer and - * glXCreatePixmap are not passed a GLXContext. - */ - bool hw_has_separate_stencil; - bool hw_must_use_separate_stencil; - bool hw_has_llc; bool hw_has_swizzling; diff --git a/src/mesa/drivers/dri/i915/intel_tex_image.c b/src/mesa/drivers/dri/i915/intel_tex_image.c index c5754c4572e..c6f3e903af9 100644 --- a/src/mesa/drivers/dri/i915/intel_tex_image.c +++ b/src/mesa/drivers/dri/i915/intel_tex_image.c @@ -367,14 +367,6 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target, if (image == NULL) return; - /* Disallow depth/stencil textures: we don't have a way to pass the - * separate stencil miptree of a GL_DEPTH_STENCIL texture through. - */ - if (image->has_depthstencil) { - _mesa_error(ctx, GL_INVALID_OPERATION, __func__); - return; - } - intel_set_texture_image_region(ctx, texImage, image->region, target, image->internal_format, image->format, image->offset, diff --git a/src/mesa/drivers/dri/i915/intel_tex_layout.c b/src/mesa/drivers/dri/i915/intel_tex_layout.c index fbb6520e7a1..eea5441b22b 100644 --- a/src/mesa/drivers/dri/i915/intel_tex_layout.c +++ b/src/mesa/drivers/dri/i915/intel_tex_layout.c @@ -74,9 +74,6 @@ intel_horizontal_texture_alignment_unit(struct intel_context *intel, return i; } - if (format == MESA_FORMAT_S8) - return 8; - /* The depth alignment requirements in the table above are for rendering to * depth miplevels using the LOD control fields. We don't use LOD control * fields, and instead use page offsets plus intra-tile x/y offsets, which @@ -123,9 +120,6 @@ intel_vertical_texture_alignment_unit(struct intel_context *intel, if (_mesa_is_format_compressed(format)) return 4; - if (format == MESA_FORMAT_S8) - return intel->gen >= 7 ? 8 : 4; - GLenum base_format = _mesa_get_format_base_format(format); if (intel->gen >= 6 &&