From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 22:58:40 +0000 (-0800)
Subject: Revert "abc9 to write_xaiger -symbols, not -map"
X-Git-Tag: working-ls180~1237^2~268
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2811d66dea8a33b6e8440db25d8bf487f70a1dc0;p=yosys.git

Revert "abc9 to write_xaiger -symbols, not -map"

This reverts commit 04429f8152ae64de050580ec20db60ac6dc1c0e1.
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 30cd68881..d652ef05a 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
 	handle_loops(design);
 
-    Pass::call(design, stringf("write_xaiger -O -symbols %s/input.xaig; ", tempdir_name.c_str()));
+    Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
 
 	// Now 'unexpose' those wires by undoing
 	// the expose operation -- remove them from PO/PI
@@ -518,7 +518,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		bool builtin_lib = liberty_file.empty();
 		RTLIL::Design *mapped_design = new RTLIL::Design;
 		//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
-		AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", "", true /* wideports */);
+		buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
+		AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
 		reader.parse_xaiger();
 
 		ifs.close();