From: Gabe Black <gabeblack@google.com>
Date: Thu, 24 Sep 2020 07:34:54 +0000 (-0700)
Subject: fastmodel: Update for the isa_traits.hh changes.
X-Git-Tag: v20.1.0.0~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=281afe2be0c1ea4f9dfea96bbc0ca1265220bd7b;p=gem5.git

fastmodel: Update for the isa_traits.hh changes.

arch/arm/isa_traits.hh no longer has using namespace ArmISA, and also
no longer directly or indirectly provides interrupt number related
constants.

Change-Id: Ieda31d1db4f85632a555b2f72ee8bff0aa159eee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35037
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 1259bf166..238beec65 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -47,11 +47,11 @@ CortexA76TC::translateAddress(Addr &paddr, Addr vaddr)
 {
     // Determine what memory spaces are currently active.
     Iris::CanonicalMsn in_msn;
-    switch (currEL(this)) {
-      case EL3:
+    switch (ArmISA::currEL(this)) {
+      case ArmISA::EL3:
         in_msn = Iris::SecureMonitorMsn;
         break;
-      case EL2:
+      case ArmISA::EL2:
         in_msn = Iris::NsHypMsn;
         break;
       default:
@@ -59,7 +59,7 @@ CortexA76TC::translateAddress(Addr &paddr, Addr vaddr)
         break;
     }
 
-    Iris::CanonicalMsn out_msn = isSecure(this) ?
+    Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
         Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
 
     // Figure out what memory spaces match the canonical numbers we need.
@@ -108,7 +108,7 @@ CortexA76TC::readIntRegFlat(RegIndex idx) const
     if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
         orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
         ArmISA::CPSR new_cpsr = orig_cpsr;
-        new_cpsr.mode = MODE_MON;
+        new_cpsr.mode = ArmISA::MODE_MON;
         non_const_this->setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr);
     }
 
@@ -129,7 +129,7 @@ CortexA76TC::setIntRegFlat(RegIndex idx, RegVal val)
     if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
         orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
         ArmISA::CPSR new_cpsr = orig_cpsr;
-        new_cpsr.mode = MODE_MON;
+        new_cpsr.mode = ArmISA::MODE_MON;
         setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr);
     }
 
@@ -146,7 +146,7 @@ CortexA76TC::readCCRegFlat(RegIndex idx) const
     RegVal result = Iris::ThreadContext::readCCRegFlat(idx);
     switch (idx) {
       case ArmISA::CCREG_NZ:
-        result = ((CPSR)result).nz;
+        result = ((ArmISA::CPSR)result).nz;
         break;
       case ArmISA::CCREG_FP:
         result = bits(result, 31, 28);
@@ -163,14 +163,14 @@ CortexA76TC::setCCRegFlat(RegIndex idx, RegVal val)
     switch (idx) {
       case ArmISA::CCREG_NZ:
         {
-            CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
+            ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
             cpsr.nz = val;
             val = cpsr;
         }
         break;
       case ArmISA::CCREG_FP:
         {
-            FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR);
+            ArmISA::FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR);
             val = insertBits(fpscr, 31, 28, val);
         }
         break;
@@ -921,10 +921,10 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::flattenedIntIdxNameMap({
         { ArmISA::INTREG_R13_FIQ, "X29" },
         { ArmISA::INTREG_R14_FIQ, "X30" },
         // Skip zero, ureg0-2, and dummy regs.
-        { INTREG_SP0, "SP_EL0" },
-        { INTREG_SP1, "SP_EL1" },
-        { INTREG_SP2, "SP_EL2" },
-        { INTREG_SP3, "SP_EL3" },
+        { ArmISA::INTREG_SP0, "SP_EL0" },
+        { ArmISA::INTREG_SP1, "SP_EL1" },
+        { ArmISA::INTREG_SP2, "SP_EL2" },
+        { ArmISA::INTREG_SP3, "SP_EL3" },
 });
 
 Iris::ThreadContext::IdxNameMap CortexA76TC::ccRegIdxNameMap({
diff --git a/src/arch/arm/fastmodel/iris/interrupts.cc b/src/arch/arm/fastmodel/iris/interrupts.cc
index 8c1f5b269..197608901 100644
--- a/src/arch/arm/fastmodel/iris/interrupts.cc
+++ b/src/arch/arm/fastmodel/iris/interrupts.cc
@@ -28,7 +28,7 @@
 #include "arch/arm/fastmodel/iris/interrupts.hh"
 
 #include "arch/arm/fastmodel/iris/thread_context.hh"
-#include "arch/arm/isa_traits.hh"
+#include "arch/arm/interrupts.hh"
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/miscregs_types.hh"
 #include "arch/arm/types.hh"
@@ -86,12 +86,12 @@ Iris::Interrupts::serialize(CheckpointOut &cp) const
     for (bool &i: interrupts)
         i = false;
 
-    interrupts[INT_ABT] = phys_abort;
-    interrupts[INT_IRQ] = phys_irq;
-    interrupts[INT_FIQ] = phys_fiq;
-    interrupts[INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX);
-    interrupts[INT_VIRT_IRQ] = virt_irq;
-    interrupts[INT_VIRT_FIQ] = virt_fiq;
+    interrupts[ArmISA::INT_ABT] = phys_abort;
+    interrupts[ArmISA::INT_IRQ] = phys_irq;
+    interrupts[ArmISA::INT_FIQ] = phys_fiq;
+    interrupts[ArmISA::INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX);
+    interrupts[ArmISA::INT_VIRT_IRQ] = virt_irq;
+    interrupts[ArmISA::INT_VIRT_FIQ] = virt_fiq;
 
     for (int i = 0; i < NumInterruptTypes; i++) {
         if (interrupts[i])