From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 10 Aug 2019 18:55:00 +0000 (-0700)
Subject: Wrong way around
X-Git-Tag: working-ls180~1149^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=282cc77604a9a855c303869321d4179790b0b64b;p=yosys.git

Wrong way around
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c803b5d3d..29510fe81 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -659,7 +659,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						break;
 				}
 				if (i > 0) {
-					cover("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
+					cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
 					cell->setPort("\\A", sig_a.extract_end(i));
 					cell->setPort("\\B", sig_b.extract_end(i));
 					cell->setPort("\\Y", sig_y.extract_end(i));
@@ -704,7 +704,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						break;
 				}
 				if (i > 0) {
-					cover_list("opt.opt_expr.fine.$alu");
+					cover("opt.opt_expr.fine.$alu");
 					cell->setPort("\\A", sig_a.extract_end(i));
 					cell->setPort("\\B", sig_b.extract_end(i));
 					cell->setPort("\\X", sig_x.extract_end(i));