From: lkcl <lkcl@web>
Date: Wed, 14 Sep 2022 17:35:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~445
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=282e3ceee2ce9f6ff41a8d155e6bc70c6fd33079;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index e89bf70c4..67c87bd4a 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -186,7 +186,8 @@ the same space):
 The SVP64 24-bit Prefix provides several options,
 all fitting within the 24-bit space (and no other). REMAP is separately
 outlined below.
-The primary options are:
+The primary options all of which are aimed at reducing instruction
+count and reducing assembler complexity are:
 
 * element-width overrides, which dynamically redefine each SFFS or SFS
   Scalar prefixed instruction to be 8-bit, 16-bit, 32-bit or 64-bit
@@ -289,6 +290,25 @@ provided in the Scalar Power ISA without one single explicit FP16 or BF16
 32-bit opcode being added.  The downside: such Scalar operations are
 all 64-bit encodings.
 
+# Vertical-First Mode
+
+This is a Computer Science term that needed first to be invented.
+There exists only one other Vertical-First Vector ISA in the world:
+Mitch Alsup's VVM Extension for the 66000.
+
+If we envisage register and Memory layout to be Horizontal and
+instructions to be vertical, and to then have some form of Loop
+System it is easier to conceptualise VF vs HF Mode:
+
+* Vertical-First progresses through *instructions* first before
+  moving on to the next *register* (or Memory-address in the case
+  of Mitch Alsup's VVM).
+* Horizontal-First (also known as Cray-style Vectors) progresses
+  through **registers** (or, register *elements* in traditional
+  Cray-Vector ISAs) in full before moving on to the next instruction.
+
+
+
 \newpage{}
 # Simple-V REMAP subsystem