From: bunnie <bunnie@kosagi.com>
Date: Wed, 27 Dec 2017 14:40:39 +0000 (+0800)
Subject: Add tracelength report generation by default to help with board layout
X-Git-Tag: 24jan2021_ls180~1780^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=282f22f09ee4796d5600787d55faea4cc9e16815;p=litex.git

Add tracelength report generation by default to help with board layout
---

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index b94b7b52..b626328e 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -119,6 +119,7 @@ class XilinxVivadoToolchain:
         tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
         tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
         tcl.append("report_io -file {}_io.rpt".format(build_name))
+        tcl.append("write_csv -force {}_tracelength.csv".format(build_name))
         tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
         tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
         tcl.append("route_design")