From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 May 2021 11:55:09 +0000 (+0100)
Subject: match up PLL names
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=28364ea8bfbd0aaaf19a90f3710facf8856c0379;p=soc.git

match up PLL names
---

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index e57bf414..f8eb0abb 100644
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -11,8 +11,8 @@ class DummyPLL(Elaboratable):
         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
         self.sel_a1_i = Signal(reset_less=True) # PLL selection
         self.clk_pll_o = Signal(reset_less=True)  # output clock
-        self.pll_18_o = Signal(reset_less=True)  # test out
-        self.pll_ana_o = Signal(reset_less=True) # analog
+        self.pll_test_o = Signal(reset_less=True)  # test out
+        self.pll_vco_o = Signal(reset_less=True) # analog
 
     def elaborate(self, platform):
         m = Module()
@@ -22,8 +22,8 @@ class DummyPLL(Elaboratable):
                                   i_a0=self.clk_sel_i[0],
                                   i_a1=self.clk_sel_i[1],
                                   o_out=self.clk_pll_o,
-                                  o_div_out_test=self.pll_18_o,
-                                  o_vco_test_ana=self.pll_ana_o,
+                                  o_div_out_test=self.pll_test_o,
+                                  o_vco_test_ana=self.pll_vco_o,
                            )
             m.submodules['pll'] = pll
             #pll.attrs['blackbox'] = 1
@@ -32,14 +32,14 @@ class DummyPLL(Elaboratable):
             # just get something, stops yosys destroying (optimising) these out
             with m.If(self.clk_sel_i == 0):
                 m.d.comb += self.pll_ana_o.eq(self.clk_24_i)
-                m.d.comb += self.pll_18_o.eq(~self.clk_24_i)
+                m.d.comb += self.pll_vco_o.eq(~self.clk_24_i)
 
 
         return m
 
     def ports(self):
         return [self.clk_24_i, self.clk_sel_i, self.clk_pll_o,
-                self.pll_18_o, self.pll_ana_o]
+                self.pll_test_o, self.pll_vco_o]
 
 
 if __name__ == '__main__':
diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index 2a473d55..e4ffa78b 160000
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit 2a473d55487fcc833744eacf82451b40728fd283
+Subproject commit e4ffa78b6ca6cc9ed8d0407c4a73394991003663
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 4aa89fcf..4e919520 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1232,7 +1232,7 @@ class TestIssuer(Elaboratable):
         # PLL direct clock or not
         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
         if self.pll_en:
-            self.pll_18_o = Signal(reset_less=True)
+            self.pll_test_o = Signal(reset_less=True)
             self.clk_sel_i = Signal(reset_less=True)
 
     def elaborate(self, platform):
@@ -1260,7 +1260,7 @@ class TestIssuer(Elaboratable):
             comb += pll.clk_24_i.eq(ClockSignal())
 
             # output 18 mhz PLL test signal
-            comb += self.pll_18_o.eq(pll.pll_18_o)
+            comb += self.pll_test_o.eq(pll.pll_test_o)
 
             # input to pll clock selection
             comb += pll.clk_sel_i.eq(self.clk_sel_i)
@@ -1289,8 +1289,8 @@ class TestIssuer(Elaboratable):
         ports.append(ResetSignal())
         if self.pll_en:
             ports.append(self.clk_sel_i)
-            ports.append(self.pll_18_o)
-            ports.append(self.pll.pll_ana_o)
+            ports.append(self.pll_test_o)
+            ports.append(self.pll.pll_vco_o)
         return ports