From: Cole Poirier <colepoirier@gmail.com>
Date: Wed, 12 Aug 2020 17:55:14 +0000 (-0700)
Subject: mmu.py add RecordObject classes from common.vhdl input types https://bugs.libre-soc... 
X-Git-Tag: semi_working_ecp5~389
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2836a2e9ae5c0672e4dbd301c8076fbeb297c0ca;p=soc.git

mmu.py add RecordObject classes from common.vhdl input types https://bugs.libre-soc.org/show_bug.cgi?id=450#c31
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 6421fec6..79f75257 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -14,6 +14,110 @@ from nmigen.iocontrol import RecordObject
 
 # library work; use work.common.all;
 
+
+# start from common.vhdl
+# type Loadstore1ToMmuType is record
+#     valid : std_ulogic;
+#     tlbie : std_ulogic;
+#     slbia : std_ulogic;
+#     mtspr : std_ulogic;
+#     iside : std_ulogic;
+#     load  : std_ulogic;
+#     priv  : std_ulogic;
+#     sprn  : std_ulogic_vector(9 downto 0);
+#     addr  : std_ulogic_vector(63 downto 0);
+#     rs    : std_ulogic_vector(63 downto 0);
+#  end record;
+class LoadStore1ToMmuType(RecordObject):
+    def __init__(self):
+        super().__init__()
+        self.valid = Signal()
+        self.tlbie = Signal()
+        self.slbia = Signal()
+        self.mtspr = Signal()
+        self.iside = Signal()
+        self.load  = Signal()
+        self.priv  = Signal()
+        self.sprn  = Signal(10)
+        self.addr  = Signal(64)
+        self.rs    = Signal(64)
+
+# type MmuToLoadstore1Type is record
+#     done       : std_ulogic;
+#     err        : std_ulogic;
+#     invalid    : std_ulogic;
+#     badtree    : std_ulogic;
+#     segerr     : std_ulogic;
+#     perm_error : std_ulogic;
+#     rc_error   : std_ulogic;
+#     sprval     : std_ulogic_vector(63 downto 0);
+# end record;
+class MmuToLoadStore1Type(RecordObject):
+    def __init__(self):
+        super().__init__()
+        self.done       = Signal()
+        self.err        = Signal()
+        self.invalid    = Signal()
+        self.badtree    = Signal()
+        self.segerr     = Signal()
+        self.perm_error = Signal()
+        self.rc_error   = Signal()
+        self.sprval     = Signal(64)
+
+# type MmuToDcacheType is record
+#     valid : std_ulogic;
+#     tlbie : std_ulogic;
+#     doall : std_ulogic;
+#     tlbld : std_ulogic;
+#     addr  : std_ulogic_vector(63 downto 0);
+#     pte   : std_ulogic_vector(63 downto 0);
+# end record;
+class MmuToDcacheType(RecordObject):
+    def __init__(self):
+        super().__init__()
+        self.valid = Signal()
+        self.tlbie = Signal()
+        self.doall = Signal()
+        self.tlbld = Signal()
+        self.addr  = Signal(64)
+        self.pte   = Signal(64)
+
+# type DcacheToMmuType is record
+#     stall : std_ulogic;
+#     done  : std_ulogic;
+#     err   : std_ulogic;
+#     data  : std_ulogic_vector(63 downto 0);
+# end record;
+class DcacheToMmuType(RecordObject):
+    def __init__(self):
+        super().__init__()
+        self.stall = Signal()
+        self.done  = Signal()
+        self.err   = Signal()
+        self.data  = Signal(64)
+
+
+# type MmuToIcacheType is record
+#    tlbld : std_ulogic;
+#    tlbie : std_ulogic;
+#    doall : std_ulogic;
+#    addr  : std_ulogic_vector(63 downto 0);
+#    pte   : std_ulogic_vector(63 downto 0);
+# end record;
+class MmuToIcacheType(RecordObject):
+    def __init__(self):
+        self.tlbld = Signal()
+        self.tlbie = Signal()
+        self.doall = Signal()
+        self.addr  = Signal(64)
+        self.pte   = Signal(64)
+# end from common.vhdl
+
+
+
+
+
+
 # -- Radix MMU
 # -- Supports 4-level trees as in arch 3.0B, but not the
 # -- two-step translation
@@ -130,8 +234,8 @@ class MMU(Elaboratable):
 #         );
 # end mmu;
     def __init__(self):
-        self.l_in  = Loadstore1ToMmuType()
-        self.l_out = MmuToLoadstore1Type()
+        self.l_in  = LoadStore1ToMmuType()
+        self.l_out = MmuToLoadStore1Type()
         self.d_out = MmuToDcacheType()
         self.d_in  = DcacheToMmuType()
         self.i_out = MmuToIcacheType()