From: Venkataramanan Kumar Date: Thu, 1 Mar 2012 09:57:59 +0000 (+0000) Subject: Document AMD bdver2 in invoke.texi X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=283b529696df97afe8ce08b14c6d62c42b7f1d28;p=gcc.git Document AMD bdver2 in invoke.texi From-SVN: r184688 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 84529c2a121..93415e93b0e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-03-01 Venkataramanan Kumar + + * doc/invoke.texi: Document AMD bdver2 and remove mentioning + 3DNow from bdver1. + 2012-02-29 Jakub Jelinek Uros Bizjak diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e57f586fe22..b806eb4670f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13084,8 +13084,12 @@ instruction set extensions.) @item bdver1 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, -SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit -instruction set extensions.) +SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) +@item bdver2 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, +SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set +extensions.) @item btver1 AMD Family 14h core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit