From: Andrew Cagney Date: Thu, 16 Oct 1997 03:39:13 +0000 (+0000) Subject: Rename generated file engine.c to oengine.c. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=284e759d1f623e92745f3ad624d455ba3baaf55a;p=binutils-gdb.git Rename generated file engine.c to oengine.c. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 1acaa730eb3..53bf2475413 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,10 @@ +Thu Oct 16 10:31:41 1997 Andrew Cagney + + * Makefile.in (interp.o): Rename generated file engine.c to + oengine.c. + + * interp.c: Update. + Thu Oct 16 10:31:40 1997 Andrew Cagney * gencode.c (build_instruction): Use FPR_STATE not fpr_state. diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index d82194f0540..fe9fb0215e1 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -44,11 +44,11 @@ SIM_RUN_OBJS = nrun.o ## COMMON_POST_CONFIG_FRAG -interp.o: $(srcdir)/interp.c engine.c config.h sim-main.h +interp.o: $(srcdir)/interp.c oengine.c config.h sim-main.h -engine.c: gencode - ./gencode @SIMCONF@ > tmp-engine - mv tmp-engine engine.c +oengine.c: gencode + ./gencode @SIMCONF@ > tmp-oengine + mv tmp-oengine oengine.c tmp.igen: gencode ./gencode --igen @SIMCONF@ > tmp-igen mv tmp-igen tmp.igen diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 1e0c35e5d87..215013aef87 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -83,7 +83,7 @@ char* pr_uword64 PARAMS ((uword64 addr)); /* Get the simulator engine description, without including the code: */ #define SIM_MANIFESTS -#include "engine.c" +#include "oengine.c" #undef SIM_MANIFESTS @@ -4195,7 +4195,7 @@ sim_engine_run (sd, next_cpu_nr, siggnal) if (!(STATE & simSKIPNEXT)) { /* Include the simulator engine */ -#include "engine.c" +#include "oengine.c" #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) #error "Mismatch between run-time simulator code and simulation engine" #endif