From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 13:56:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2920
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=285f047c9c4667d853174c286251e424c0cb96f7;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 12327582a..405ee1670 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -491,13 +491,14 @@ in SVP64 when LRu=1).
 ```
 if (mode_is_64bit) then M <- 0
 else M <- 32
+testbit = CR[BI+32]
+if ¬predicate_bit then testbit = SVRMmode.SNZ
 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
-cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
+cond_ok <- BO[0] | ¬(testbit ^ BO[1])
 if ¬predicate_bit & ¬SVRMmode.sz then
-  if ¬BO[2] & CTRtest & ¬CTI then
+  if ¬BO[2] & CTRtest & ¬CTi then
     CTR = CTR - 1
   stop # instruction finishes here
-if ¬predicate_bit then cond_ok = ctr_ok = SVRMmode.SNZ
 if ¬BO[2] & ¬(CTRtest & (cond_ok ^ CTi)) then CTR <- CTR - 1
 lr_ok <- SVRMmode.LRu
 if ctr_ok & cond_ok then