From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 10:42:06 +0000 (+0200)
Subject: Cleaned tests
X-Git-Tag: working-ls180~987^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=286a2728729a6cf4b65afec6dbe65d269f1a5ca6;p=yosys.git

Cleaned tests
---

diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v
index 0605bd102..368fbaace 100644
--- a/tests/efinix/fsm.v
+++ b/tests/efinix/fsm.v
@@ -52,22 +52,4 @@
  endcase
  end
 
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
 endmodule
diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys
index 9de6aa280..2ec75215d 100644
--- a/tests/efinix/fsm.ys
+++ b/tests/efinix/fsm.ys
@@ -1,12 +1,12 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
 flatten
 #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
 #equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1  t:EFX_GBUFCE
 select -assert-count 6  t:EFX_FF
diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v
index c55632552..ce2c81dd2 100644
--- a/tests/efinix/shifter.v
+++ b/tests/efinix/shifter.v
@@ -9,14 +9,8 @@ in
 
     always @(posedge clk)
 	begin
-`ifndef BUG
-		out    <= out >> 1;
-		out[7] <= in;
-`else
-
 		out    <= out << 1;
 		out[7] <= in;
-`endif
 	end
 
 endmodule
diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v
index 3fa6eb6c6..c64468253 100644
--- a/tests/efinix/tribuf.v
+++ b/tests/efinix/tribuf.v
@@ -2,28 +2,7 @@ module tristate (en, i, o);
     input en;
     input i;
     output reg o;
-`ifndef BUG 
     
     always @(en or i)
 		o <= (en)? i : 1'bZ;
-`else
-	
-    always @(en or i)
-		o <= (en)? ~i : 1'bZ;
-`endif
-endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
 endmodule
diff --git a/tests/efinix/tribuf.ys b/tests/efinix/tribuf.ys
index 20d4f215d..2e2ab9e65 100644
--- a/tests/efinix/tribuf.ys
+++ b/tests/efinix/tribuf.ys
@@ -1,12 +1,12 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 tribuf
 flatten
 synth
 equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D