From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Mar 2019 05:41:02 +0000 (+0000)
Subject: forgot to add submodules
X-Git-Tag: ls180-24jan2020~1665
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e;p=ieee754fpu.git

forgot to add submodules
---

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 8ddd45eb..130d49e8 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -28,6 +28,10 @@ class FPMUL(FPBase):
         product = Signal(mw)
 
         of = Overflow()
+        m.submodules.of = of
+        m.submodules.a = a
+        m.submodules.b = b
+        m.submodules.z = z
 
         with m.FSM() as fsm:
 
@@ -127,7 +131,7 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of)
+                self.roundz(m, z, of.roundz)
                 m.next = "corrections"
 
             # ******
diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index db95dccc..db95eb13 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -558,10 +558,10 @@ class FPBase:
         with m.Else():
             m.next = next_state
 
-    def roundz(self, m, z, of):
+    def roundz(self, m, z, roundz):
         """ performs rounding on the output.  TODO: different kinds of rounding
         """
-        with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])):
+        with m.If(roundz):
             m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
             with m.If(z.m == z.m1s): # all 1s
                 m.d.sync += z.e.eq(z.e + 1) # exponent rounds up