From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Fri, 11 Aug 2017 23:16:25 +0000 (-0700)
Subject: Fixed handling of cell ports that aren't wires
X-Git-Tag: yosys-0.8~345^2~1^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2877d5e50449dd08ebcb183218d015008c9fffcb;p=yosys.git

Fixed handling of cell ports that aren't wires
---

diff --git a/passes/opt/opt_rmports.cc b/passes/opt/opt_rmports.cc
index afbbecf84..5522dfa8e 100644
--- a/passes/opt/opt_rmports.cc
+++ b/passes/opt/opt_rmports.cc
@@ -90,6 +90,9 @@ struct OptRmportsPass : public Pass {
 				for(int i=0; i<conn.second.size(); i++)
 				{
 					auto sig = conn.second[i].wire;
+					if(sig == NULL)
+						continue;
+
 					//log("  sig %s\n", sig->name.c_str());
 					if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
 						used_ports.emplace(sig->name);