From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 3 Jul 2017 12:53:17 +0000 (+0200)
Subject: Include output ports with constant driver in AIGER output
X-Git-Tag: yosys-0.8~406
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=287831dca36b1098165abd2381b35f81b2c0e312;p=yosys.git

Include output ports with constant driver in AIGER output
---

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 5bf5a4c58..de0509930 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -112,10 +112,20 @@ struct AigerWriter
 						init_map[initsig[i]] = initval[i] == State::S1;
 			}
 
+			int index = 0;
 			for (auto bit : sigmap(wire))
 			{
 				if (bit.wire == nullptr)
+				{
+					if (wire->port_output) {
+						SigBit wirebit(wire, index);
+						aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
+						output_bits.insert(wirebit);
+					}
+
+					index++;
 					continue;
+				}
 
 				undriven_bits.insert(bit);
 				unused_bits.insert(bit);
@@ -125,6 +135,8 @@ struct AigerWriter
 
 				if (wire->port_output)
 					output_bits.insert(bit);
+
+				index++;
 			}
 		}
 
@@ -495,8 +507,12 @@ struct AigerWriter
 
 				for (int i = 0; i < GetSize(wire); i++)
 				{
-					if (sig[i].wire == nullptr)
-						continue;
+					if (sig[i].wire == nullptr) {
+						if (wire->port_output)
+							sig[i] = SigBit(wire, i);
+						else
+							continue;
+					}
 
 					if (wire->port_input) {
 						int a = aig_map.at(sig[i]);