From: Andreas Hansson Date: Fri, 7 Sep 2012 16:34:38 +0000 (-0400) Subject: Param: Transition to Cycles for relevant parameters X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=287ea1a081c5dd3213069755dbbd3d7bf736bacc;p=gem5.git Param: Transition to Cycles for relevant parameters This patch is a first step to using Cycles as a parameter type. The main affected modules are the CPUs and the Ruby caches. There are definitely plenty more places that are affected, but this patch serves as a starting point to making the transition. An important part of this patch is to actually enable parameters to be specified as Param.Cycles which involves some changes to params.py. --- diff --git a/src/base/types.hh b/src/base/types.hh index 4caf92c97..7f4375048 100644 --- a/src/base/types.hh +++ b/src/base/types.hh @@ -89,6 +89,9 @@ class Cycles /** Explicit constructor assigning a value. */ explicit Cycles(uint64_t _c) : c(_c) { } + /** Default constructor for parameter classes. */ + Cycles() : c(0) { } + #ifndef SWIG // keep the operators away from SWIG /** Converting back to the value type. */ diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index 002546f26..92d7e13ca 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -53,9 +53,9 @@ class OpClass(Enum): class OpDesc(SimObject): type = 'OpDesc' - issueLat = Param.Int(1, "cycles until another can be issued") + issueLat = Param.Cycles(1, "cycles until another can be issued") opClass = Param.OpClass("type of operation") - opLat = Param.Int(1, "cycles until result is available") + opLat = Param.Cycles(1, "cycles until result is available") class FUDesc(SimObject): type = 'FUDesc' diff --git a/src/cpu/func_unit.hh b/src/cpu/func_unit.hh index 3745bb7d1..51e2011f8 100644 --- a/src/cpu/func_unit.hh +++ b/src/cpu/func_unit.hh @@ -51,8 +51,8 @@ class OpDesc : public SimObject { public: OpClass opClass; - unsigned opLat; - unsigned issueLat; + Cycles opLat; + Cycles issueLat; OpDesc(const OpDescParams *p) : SimObject(p), opClass(p->opClass), opLat(p->opLat), diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 416b18dd3..119de7f1c 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -65,13 +65,13 @@ class InOrderCPU(BaseCPU): stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU") - multLatency = Param.Unsigned(1, "Latency for Multiply Operations") - multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations") - div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations") - div8RepeatRate = Param.Unsigned(1, "Repeat Rate for 8-bit Divide Operations") - div16Latency = Param.Unsigned(1, "Latency for 16-bit Divide Operations") - div16RepeatRate = Param.Unsigned(1, "Repeat Rate for 16-bit Divide Operations") - div24Latency = Param.Unsigned(1, "Latency for 24-bit Divide Operations") - div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide Operations") - div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations") - div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide Operations") + multLatency = Param.Cycles(1, "Latency for Multiply Operations") + multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations") + div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations") + div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations") + div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations") + div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide Operations") + div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations") + div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide Operations") + div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations") + div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations") diff --git a/src/cpu/inorder/params.hh b/src/cpu/inorder/params.hh index 44f2a5018..a4ffdf70b 100644 --- a/src/cpu/inorder/params.hh +++ b/src/cpu/inorder/params.hh @@ -97,24 +97,24 @@ class InOrderParams : public BaseCPU::Params // then MDU must be defined as its own SimObject so that an arbitrary # can // be defined with different parameters /** Latency & Repeat Rate for Multiply Insts */ - unsigned multLatency; - unsigned multRepeatRate; + Cycles multLatency; + Cycles multRepeatRate; /** Latency & Repeat Rate for 8-bit Divide Insts */ - unsigned div8Latency; - unsigned div8RepeatRate; + Cycles div8Latency; + Cycles div8RepeatRate; /** Latency & Repeat Rate for 16-bit Divide Insts */ - unsigned div16Latency; - unsigned div16RepeatRate; + Cycles div16Latency; + Cycles div16RepeatRate; /** Latency & Repeat Rate for 24-bit Divide Insts */ - unsigned div24Latency; - unsigned div24RepeatRate; + Cycles div24Latency; + Cycles div24RepeatRate; /** Latency & Repeat Rate for 32-bit Divide Insts */ - unsigned div32Latency; - unsigned div32RepeatRate; + Cycles div32Latency; + Cycles div32RepeatRate; }; diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 9306cb44e..6923e7b25 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -39,31 +39,31 @@ class DerivO3CPU(BaseCPU): cachePorts = Param.Unsigned(200, "Cache Ports") - decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") - renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") - iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") + decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") + renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") + iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") fetchWidth = Param.Unsigned(8, "Fetch width") - renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") - iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") + renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") + iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " + "delay") + commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") + fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") decodeWidth = Param.Unsigned(8, "Decode width") - iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") - decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") + iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " + "delay") + commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") + decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") renameWidth = Param.Unsigned(8, "Rename width") - commitToIEWDelay = Param.Unsigned(1, "Commit to " + commitToIEWDelay = Param.Cycles(1, "Commit to " "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned(2, "Rename to " + renameToIEWDelay = Param.Cycles(2, "Rename to " "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " + issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " "to the IEW stage)") dispatchWidth = Param.Unsigned(8, "Dispatch width") issueWidth = Param.Unsigned(8, "Issue width") @@ -71,13 +71,13 @@ class DerivO3CPU(BaseCPU): wbDepth = Param.Unsigned(1, "Writeback depth") fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") - iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " + iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " "delay") - renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") + renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") commitWidth = Param.Unsigned(8, "Commit width") squashWidth = Param.Unsigned(8, "Squash width") - trapLatency = Param.Unsigned(13, "Trap latency") - fetchTrapLatency = Param.Unsigned(1, "Fetch trap latency") + trapLatency = Param.Cycles(13, "Trap latency") + fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index d30097553..d3d1ad347 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -375,16 +375,16 @@ class DefaultCommit /** Priority List used for Commit Policy */ std::list priority_list; - /** IEW to Commit delay, in ticks. */ - unsigned iewToCommitDelay; + /** IEW to Commit delay. */ + Cycles iewToCommitDelay; - /** Commit to IEW delay, in ticks. */ - unsigned commitToIEWDelay; + /** Commit to IEW delay. */ + Cycles commitToIEWDelay; - /** Rename to ROB delay, in ticks. */ - unsigned renameToROBDelay; + /** Rename to ROB delay. */ + Cycles renameToROBDelay; - unsigned fetchToCommitDelay; + Cycles fetchToCommitDelay; /** Rename width, in instructions. Used so ROB knows how many * instructions to get from the rename instruction queue. diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh index 663831254..817c5263f 100644 --- a/src/cpu/o3/decode.hh +++ b/src/cpu/o3/decode.hh @@ -244,17 +244,17 @@ class DefaultDecode /** Tracks which stages are telling decode to stall. */ Stalls stalls[Impl::MaxThreads]; - /** Rename to decode delay, in ticks. */ - unsigned renameToDecodeDelay; + /** Rename to decode delay. */ + Cycles renameToDecodeDelay; - /** IEW to decode delay, in ticks. */ - unsigned iewToDecodeDelay; + /** IEW to decode delay. */ + Cycles iewToDecodeDelay; - /** Commit to decode delay, in ticks. */ - unsigned commitToDecodeDelay; + /** Commit to decode delay. */ + Cycles commitToDecodeDelay; - /** Fetch to decode delay, in ticks. */ - unsigned fetchToDecodeDelay; + /** Fetch to decode delay. */ + Cycles fetchToDecodeDelay; /** The width of decode, in instructions. */ unsigned decodeWidth; diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 6bf5f4588..42ea5cb71 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -428,17 +428,17 @@ class DefaultFetch /** Tracks which stages are telling fetch to stall. */ Stalls stalls[Impl::MaxThreads]; - /** Decode to fetch delay, in ticks. */ - unsigned decodeToFetchDelay; + /** Decode to fetch delay. */ + Cycles decodeToFetchDelay; - /** Rename to fetch delay, in ticks. */ - unsigned renameToFetchDelay; + /** Rename to fetch delay. */ + Cycles renameToFetchDelay; - /** IEW to fetch delay, in ticks. */ - unsigned iewToFetchDelay; + /** IEW to fetch delay. */ + Cycles iewToFetchDelay; - /** Commit to fetch delay, in ticks. */ - unsigned commitToFetchDelay; + /** Commit to fetch delay. */ + Cycles commitToFetchDelay; /** The width of fetch in instructions. */ unsigned fetchWidth; diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc index 3f0e46543..ecbd79ee7 100644 --- a/src/cpu/o3/fu_pool.cc +++ b/src/cpu/o3/fu_pool.cc @@ -76,8 +76,8 @@ FUPool::FUPool(const Params *p) funcUnits.clear(); for (int i = 0; i < Num_OpClasses; ++i) { - maxOpLatencies[i] = 0; - maxIssueLatencies[i] = 0; + maxOpLatencies[i] = Cycles(0); + maxIssueLatencies[i] = Cycles(0); } // @@ -149,7 +149,7 @@ FUPool::FUPool(const Params *p) } void -FUPool::annotateMemoryUnits(unsigned hit_latency) +FUPool::annotateMemoryUnits(Cycles hit_latency) { maxOpLatencies[MemReadOp] = hit_latency; diff --git a/src/cpu/o3/fu_pool.hh b/src/cpu/o3/fu_pool.hh index 66804b534..fbdc1d89a 100644 --- a/src/cpu/o3/fu_pool.hh +++ b/src/cpu/o3/fu_pool.hh @@ -59,9 +59,9 @@ class FUPool : public SimObject { private: /** Maximum op execution latencies, per op class. */ - unsigned maxOpLatencies[Num_OpClasses]; + Cycles maxOpLatencies[Num_OpClasses]; /** Maximum issue latencies, per op class. */ - unsigned maxIssueLatencies[Num_OpClasses]; + Cycles maxIssueLatencies[Num_OpClasses]; /** Bitvector listing capabilities of this FU pool. */ std::bitset capabilityList; @@ -124,7 +124,7 @@ class FUPool : public SimObject /** Annotates units that provide memory operations. Included only because * old FU pool provided this function. */ - void annotateMemoryUnits(unsigned hit_latency); + void annotateMemoryUnits(Cycles hit_latency); /** * Gets a FU providing the requested capability. Will mark the unit as busy, @@ -148,12 +148,12 @@ class FUPool : public SimObject void dump(); /** Returns the operation execution latency of the given capability. */ - unsigned getOpLatency(OpClass capability) { + Cycles getOpLatency(OpClass capability) { return maxOpLatencies[capability]; } /** Returns the issue latency of the given capability. */ - unsigned getIssueLatency(OpClass capability) { + Cycles getIssueLatency(OpClass capability) { return maxIssueLatencies[capability]; } diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index adb797525..0a519996d 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -419,18 +419,18 @@ class DefaultIEW */ bool updatedQueues; - /** Commit to IEW delay, in ticks. */ - unsigned commitToIEWDelay; + /** Commit to IEW delay. */ + Cycles commitToIEWDelay; - /** Rename to IEW delay, in ticks. */ - unsigned renameToIEWDelay; + /** Rename to IEW delay. */ + Cycles renameToIEWDelay; /** - * Issue to execute delay, in ticks. What this actually represents is + * Issue to execute delay. What this actually represents is * the amount of time it takes for an instruction to wake up, be * scheduled, and sent to a FU for execution. */ - unsigned issueToExecuteDelay; + Cycles issueToExecuteDelay; /** Width of dispatch, in instructions. */ unsigned dispatchWidth; diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index 9ceab1525..42a244c0a 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -426,7 +426,7 @@ class InstructionQueue /** Delay between commit stage and the IQ. * @todo: Make there be a distinction between the delays within IEW. */ - unsigned commitToIEWDelay; + Cycles commitToIEWDelay; /** Is the IQ switched out. */ bool switchedOut; diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index a8f14287a..785f86676 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -800,7 +800,7 @@ InstructionQueue::scheduleReadyInsts() } int idx = -2; - int op_latency = 1; + Cycles op_latency = Cycles(1); ThreadID tid = issuing_inst->threadNumber; if (op_class != No_OpClass) { @@ -814,7 +814,7 @@ InstructionQueue::scheduleReadyInsts() // If we have an instruction that doesn't require a FU, or a // valid FU, then schedule for execution. if (idx == -2 || idx != -1) { - if (op_latency == 1) { + if (op_latency == Cycles(1)) { i2e_info->size++; instsToExecute.push_back(issuing_inst); @@ -823,7 +823,7 @@ InstructionQueue::scheduleReadyInsts() if (idx >= 0) fuPool->freeUnitNextCycle(idx); } else { - int issue_latency = fuPool->getIssueLatency(op_class); + Cycles issue_latency = fuPool->getIssueLatency(op_class); // Generate completion event for the FU FUCompletion *execution = new FUCompletion(issuing_inst, idx, this); @@ -832,7 +832,7 @@ InstructionQueue::scheduleReadyInsts() cpu->clockEdge(Cycles(op_latency - 1))); // @todo: Enforce that issue_latency == 1 or op_latency - if (issue_latency > 1) { + if (issue_latency > Cycles(1)) { // If FU isn't pipelined, then it must be freed // upon the execution completing. execution->setFreeFU(); diff --git a/src/mem/Bus.py b/src/mem/Bus.py index b398af959..d24cefa62 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -49,7 +49,7 @@ class BaseBus(MemObject): master = VectorMasterPort("vector port for connecting slaves") # Override the default clock clock = '1GHz' - header_cycles = Param.Int(1, "cycles of overhead per transaction") + header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Int(8, "bus width (bytes)") block_size = Param.Int(64, "The default block size if not set by " \ "any connected module") diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 83b3c70c2..081a0f15e 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -37,7 +37,7 @@ class BaseCache(MemObject): assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") latency = Param.Latency("Latency") - hash_delay = Param.Int(1, "time in cycles of hash access") + hash_delay = Param.Cycles(1, "time in cycles of hash access") max_miss_count = Param.Counter(0, "number of misses to handle before calling exit") mshrs = Param.Int("number of MSHRs (max outstanding requests)") diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index d6ddf04a6..3fdc11e80 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -250,6 +250,8 @@ IIC::accessBlock(Addr addr, int &lat, int context_src) } } + // @todo: is hashDelay is really cycles, then + // multiply with period set_lat = set_lat * hashDelay + hitLatency; if (tag_ptr != NULL) { // IIC replacement: if this is not the first element of diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 0c3ea7a13..fd63daff7 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -196,7 +196,7 @@ class IIC : public BaseTags const unsigned subMask; /** The latency of a hash lookup. */ - const unsigned hashDelay; + const Cycles hashDelay; /** The total number of tags in primary and secondary. */ const unsigned numTags; /** The number of tags in the secondary tag store. */ diff --git a/src/mem/ruby/system/BankedArray.cc b/src/mem/ruby/system/BankedArray.cc index b7efa7d56..8af0701a5 100644 --- a/src/mem/ruby/system/BankedArray.cc +++ b/src/mem/ruby/system/BankedArray.cc @@ -36,7 +36,7 @@ #include "mem/ruby/system/BankedArray.hh" #include "sim/eventq.hh" -BankedArray::BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit) : +BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit) : EventManager(&mainEventQueue) { this->banks = banks; diff --git a/src/mem/ruby/system/BankedArray.hh b/src/mem/ruby/system/BankedArray.hh index 15c2d2c15..7ebf39dfb 100644 --- a/src/mem/ruby/system/BankedArray.hh +++ b/src/mem/ruby/system/BankedArray.hh @@ -43,7 +43,7 @@ class BankedArray : public EventManager { private: unsigned int banks; - unsigned int accessLatency; + Cycles accessLatency; unsigned int bankBits; unsigned int startIndexBit; @@ -66,7 +66,7 @@ private: unsigned int mapIndexToBank(Index idx); public: - BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit); + BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit); // Note: We try the access based on the cache index, not the address // This is so we don't get aliasing on blocks being replaced diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py index 2b4daa68b..57326c3c6 100644 --- a/src/mem/ruby/system/Cache.py +++ b/src/mem/ruby/system/Cache.py @@ -43,6 +43,6 @@ class RubyCache(SimObject): dataArrayBanks = Param.Int(1, "Number of banks for the data array") tagArrayBanks = Param.Int(1, "Number of banks for the tag array") - dataAccessLatency = Param.Int(1, "Gem5 cycles for the data array") - tagAccessLatency = Param.Int(1, "Gem5 cycles for the tag array") + dataAccessLatency = Param.Cycles(1, "cycles for a data array access") + tagAccessLatency = Param.Cycles(1, "cycles for a tag array access") resourceStalls = Param.Bool(False, "stall if there is a resource failure") diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index dbdfca38e..cc63a93a4 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -139,7 +139,7 @@ class Sequencer : public RubyPort private: int m_max_outstanding_requests; - int m_deadlock_threshold; + Cycles m_deadlock_threshold; CacheMemory* m_dataCache_ptr; CacheMemory* m_instCache_ptr; diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 79cf9709e..deef6e714 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -58,7 +58,7 @@ class RubySequencer(RubyPort): dcache = Param.RubyCache("") max_outstanding_requests = Param.Int(16, "max requests (incl. prefetches) outstanding") - deadlock_threshold = Param.Int(500000, + deadlock_threshold = Param.Cycles(500000, "max outstanding cycles for a request before deadlock/livelock declared") class DMASequencer(RubyPort): diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 5c40a9c64..c2da6171e 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -463,8 +463,6 @@ class CheckedInt(NumericParamValue): # most derived types require this, so we just do it here once code('%import "stdint.i"') code('%import "base/types.hh"') - # ignore the case operator for Cycles - code('%ignore *::operator uint64_t() const;') def getValue(self): return long(self.value) @@ -482,13 +480,21 @@ class Int64(CheckedInt): cxx_type = 'int64_t'; size = 64; unsigned = False class UInt64(CheckedInt): cxx_type = 'uint64_t'; size = 64; unsigned = True class Counter(CheckedInt): cxx_type = 'Counter'; size = 64; unsigned = True -class Cycles(CheckedInt): cxx_type = 'Cycles'; size = 64; unsigned = True class Tick(CheckedInt): cxx_type = 'Tick'; size = 64; unsigned = True class TcpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 +class Cycles(CheckedInt): + cxx_type = 'Cycles' + size = 64 + unsigned = True + + def getValue(self): + from m5.internal.core import Cycles + return Cycles(self.value) + class Float(ParamValue, float): cxx_type = 'double'