From: lkcl <lkcl@web>
Date: Thu, 8 Sep 2022 00:11:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~644
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2892346742338553765dd27273ac7b2fa22569b0;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 93ec30add..632f3488a 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -84,10 +84,11 @@ it is possible to service Precise Interrupts without affecting latency
 * normal Vector ISAs use either Indexed-MV or Indexed-LD/ST to "cope"
   with this.  both are expensive (copy large vectors, spill through memory)
   and very few Packed SIMD ISAs cope with non-Power-2.
-* REMAP **redefines** the order of access according to set "Schedules".
-* The Schedules are not necessarily restricted to power-of-two boundaries
+* REMAP **redefines** the order of access according to set
+  (Deterministic) "Schedules".
+* The Schedules are not at all restricted to power-of-two boundaries
   making it unnecessary to have for example specialised 3x4 transpose
-  instructions.
+  instructions of other Vector ISAs.
 
 Only the most commonly-used algorithms in computer science have REMAP
 support, due to the high cost in both the ISA and in hardware.  For