From: Miodrag Milanovic Date: Sun, 11 Aug 2019 15:05:24 +0000 (+0200) Subject: Fix formating X-Git-Tag: working-ls180~1116^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2897fe4d09118e37934b7e76f4990cc1d69a0cb5;p=yosys.git Fix formating --- diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index 56e1b039f..178f57bc5 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -33,8 +33,8 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; - wire CIx; - wire [Y_WIDTH-1:0] COx; + wire CIx; + wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;