From: Luke Kenneth Casson Leighton Date: Thu, 1 Aug 2019 07:49:08 +0000 (+0100) Subject: move priority picker to nmutil X-Git-Tag: div_pipeline~1831 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=289beee62a3b324aea8dd3e163fb6e444421ac8d;p=soc.git move priority picker to nmutil --- diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py index 133b3720..a59fdd28 100644 --- a/src/scoreboard/group_picker.py +++ b/src/scoreboard/group_picker.py @@ -1,7 +1,3 @@ -from nmigen.compat.sim import run_simulation -from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Cat, Elaboratable - """ Group Picker: to select an instruction that is permitted to read (or write) based on the Function Unit expressing a *desire* to read (or write). @@ -46,40 +42,11 @@ from nmigen import Module, Signal, Cat, Elaboratable """ -class PriorityPicker(Elaboratable): - """ implements a priority-picker. input: N bits, output: N bits - """ - def __init__(self, wid): - self.wid = wid - # inputs - self.i = Signal(wid, reset_less=True) - self.o = Signal(wid, reset_less=True) - - def elaborate(self, platform): - m = Module() - - res = [] - ni = Signal(self.wid, reset_less = True) - m.d.comb += ni.eq(~self.i) - for i in range(0, self.wid): - t = Signal(reset_less = True) - res.append(t) - if i == 0: - m.d.comb += t.eq(self.i[i]) - else: - m.d.comb += t.eq(~Cat(ni[i], *self.i[:i]).bool()) - - # we like Cat(*xxx). turn lists into concatenated bits - m.d.comb += self.o.eq(Cat(*res)) - - return m - - def __iter__(self): - yield self.i - yield self.o +from nmigen.compat.sim import run_simulation +from nmigen.cli import verilog, rtlil +from nmigen import Module, Signal, Elaboratable - def ports(self): - return list(self) +from nmutil.picker import PriorityPicker class GroupPicker(Elaboratable):