From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 16:02:29 +0000 (-0700)
Subject: Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
X-Git-Tag: working-ls180~1039^2~61
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=289cf688b76328d62c7416d1327d2d6777b0ffd9;p=yosys.git

Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
---

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 284bc90d0..7a8f3d70c 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -274,9 +274,8 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 			if (help_mode || dsp) {
 				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
-						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
 						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("opt_expr -fine", "               (if -dsp)");
 				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6687a0786..022b0d108 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -343,7 +343,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 "
-						"-D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
 						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
 						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 				run("xilinx_dsp");