From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 19 Sep 2023 15:42:48 +0000 (+0100)
Subject: Added english description for lhzu instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=28afbcdf7fcc71c68d8410fbb6e9a85266d746d3;p=openpower-isa.git

Added english description for lhzu instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 500489b7..0e2b6536 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -152,6 +152,10 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
+Description:Let the effective address (EA) be the sum
+(RA|0)+ (RB). The halfword in storage addressed by
+EA is loaded into RT 48:63. RT 0:47 are set to 0.
+
 Special Registers Altered:
 
     None