From: Udi Finkelstein <github@udifink.com>
Date: Wed, 15 Aug 2018 16:56:30 +0000 (+0300)
Subject: A few minor enhancements to specify block parsing.
X-Git-Tag: yosys-0.8~22^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=28cfc75a902574c3ad96876d2f5e01af6c583bac;p=yosys.git

A few minor enhancements to specify block parsing.
Just remember specify blocks are parsed but ignored.
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 78cac5543..61da12b76 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -688,8 +688,8 @@ path_declaration :
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value ';'
-	// | full_path_description '=' path_delay_value ';'
+	parallel_path_description '=' path_delay_value ';' |
+	full_path_description '=' path_delay_value ';'
 	;
 
 path_delay_value :
@@ -723,6 +723,17 @@ list_of_path_delay_expressions :
 parallel_path_description :
 	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
+full_path_description :
+	'(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+
+list_of_path_inputs :
+	specify_input_terminal_descriptor |
+	list_of_path_inputs ',' specify_input_terminal_descriptor ;
+	
+list_of_path_outputs :
+	specify_output_terminal_descriptor |
+	list_of_path_outputs ',' specify_output_terminal_descriptor ;
+	
 opt_polarity_operator :
 	'+'
 	| '-'