From: Michael Nolan <mtnolan2640@gmail.com>
Date: Tue, 19 May 2020 15:06:04 +0000 (-0400)
Subject: Handle carry out in alu
X-Git-Tag: div_pipeline~1080
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=28e87bd8737a589291e1ed710036934d9412ef04;p=soc.git

Handle carry out in alu
---

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 20f00d6e..24a47ce7 100644
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -37,6 +37,10 @@ class ALUOutputStage(PipeModBase):
         with m.Else():
             comb += target.eq(o)
 
+        # Handle carry_out
+        with m.If(self.i.ctx.op.output_carry):
+            comb += self.o.carry_out.eq(self.i.carry_out)
+
         # create condition register cr0 and sticky-overflow
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)
diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 138ad3e1..94fcad78 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -124,14 +124,15 @@ class ALUTestCase(FHDLTestCase):
 
     def test_adde(self):
         lst = ["adde. 5, 6, 7"]
-        initial_regs = [0] * 32
-        initial_regs[6] = random.randint(0, (1<<64)-1)
-        initial_regs[7] = random.randint(0, (1<<64)-1)
-        initial_sprs = {}
-        xer = SelectableInt(0, 64)
-        xer[XER_bits['CA']] = 1
-        initial_sprs[special_sprs['XER']] = xer
-        self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+        for i in range(10):
+            initial_regs = [0] * 32
+            initial_regs[6] = random.randint(0, (1<<64)-1)
+            initial_regs[7] = random.randint(0, (1<<64)-1)
+            initial_sprs = {}
+            xer = SelectableInt(0, 64)
+            xer[XER_bits['CA']] = 1
+            initial_sprs[special_sprs['XER']] = xer
+            self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 
     def test_cmp(self):
         lst = ["subf. 1, 6, 7",
@@ -259,6 +260,12 @@ class TestRunner(FHDLTestCase):
             cr_expected = sim.crl[bf].get_range().value
             self.assertEqual(cr_expected, cr_actual, code)
 
+        cry_out = yield dec2.e.output_carry
+        if cry_out:
+            expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+            real_carry = yield alu.n.data_o.carry_out
+            self.assertEqual(expected_carry, real_carry)
+
 
 
 if __name__ == "__main__":