From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 1 Apr 2015 16:14:56 +0000 (+0800)
Subject: soc: use set
X-Git-Tag: 24jan2021_ls180~2408
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2900429e6560b091f4e3e1ad703425937d6ff41e;p=litex.git

soc: use set
---

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index babd6624..52e93dd8 100644
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -160,7 +160,7 @@ class SoC(Module):
 		return self._csr_regions
 
 	def do_finalize(self):
-		registered_mems = [regions[0] for regions in self._memory_regions]
+		registered_mems = {regions[0] for regions in self._memory_regions}
 		if self.cpu_type != "none":
 			for mem in "rom", "sram":
 				if mem not in registered_mems: