From: Jan Beulich Date: Thu, 8 Mar 2018 07:26:35 +0000 (+0100) Subject: x86: bogus VMOVD with 64-bit operands should only allow for registers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2907c2f55555de6b1df9a0262629003f4856807d;p=binutils-gdb.git x86: bogus VMOVD with 64-bit operands should only allow for registers These templates exist solely to satisfy gcc's needs, and gcc only produces these with register operands. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 564a2690424..6a1d0a2db9f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2018-03-08 Jan Beulich + + * testsuite/gas/i386/x86-64-movd.s: Drop bogus vmovd memory forms. + * testsuite/gas/i386/x86-64-movd.d, + testsuite/gas/i386/x86-64-movd-intel.d: Adjust expectations. + 2018-03-08 Jan Beulich * config/tc-i386.c (operand_type_and_not): New. diff --git a/gas/testsuite/gas/i386/x86-64-movd-intel.d b/gas/testsuite/gas/i386/x86-64-movd-intel.d index fe99f626fe8..dac21c8752d 100644 --- a/gas/testsuite/gas/i386/x86-64-movd-intel.d +++ b/gas/testsuite/gas/i386/x86-64-movd-intel.d @@ -40,8 +40,6 @@ Disassembly of section .text: +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR \[rax\+0x80\],xmm1 +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR \[rax\+0x80\],xmm1 +[a-f0-9]+: 62 f1 7d 08 7e c8 vmovd eax,xmm1 - +[a-f0-9]+: c4 e1 f9 6e 88 80 00 00 00 vmovq xmm1,QWORD PTR \[rax\+0x80\] +[a-f0-9]+: c4 e1 f9 6e c8 vmovq xmm1,rax - +[a-f0-9]+: c4 e1 f9 7e 88 80 00 00 00 vmovq QWORD PTR \[rax\+0x80\],xmm1 +[a-f0-9]+: c4 e1 f9 7e c8 vmovq rax,xmm1 #pass diff --git a/gas/testsuite/gas/i386/x86-64-movd.d b/gas/testsuite/gas/i386/x86-64-movd.d index 5d4a6c61e8c..b034c331cf8 100644 --- a/gas/testsuite/gas/i386/x86-64-movd.d +++ b/gas/testsuite/gas/i386/x86-64-movd.d @@ -39,8 +39,6 @@ Disassembly of section .text: +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd %xmm1,0x80\(%rax\) +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd %xmm1,0x80\(%rax\) +[a-f0-9]+: 62 f1 7d 08 7e c8 vmovd %xmm1,%eax - +[a-f0-9]+: c4 e1 f9 6e 88 80 00 00 00 vmovq 0x80\(%rax\),%xmm1 +[a-f0-9]+: c4 e1 f9 6e c8 vmovq %rax,%xmm1 - +[a-f0-9]+: c4 e1 f9 7e 88 80 00 00 00 vmovq %xmm1,0x80\(%rax\) +[a-f0-9]+: c4 e1 f9 7e c8 vmovq %xmm1,%rax #pass diff --git a/gas/testsuite/gas/i386/x86-64-movd.s b/gas/testsuite/gas/i386/x86-64-movd.s index 1722cef2a3a..7d79768528e 100644 --- a/gas/testsuite/gas/i386/x86-64-movd.s +++ b/gas/testsuite/gas/i386/x86-64-movd.s @@ -35,7 +35,5 @@ _start: {evex} vmovd dword ptr [rax + 128], xmm1 {evex} vmovd [rax + 128], xmm1 {evex} vmovd eax, xmm1 - vmovd xmm1, qword ptr [rax + 128] vmovd xmm1, rax - vmovd qword ptr [rax + 128], xmm1 vmovd rax, xmm1 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index da0d7e2953e..309a034bfc7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-03-08 Jan Beulich + + * i386-opc.tbl (vmovd): Disallow Qword memory operands. + * i386-tlb.h: Re-generate. + 2018-03-08 Jan Beulich * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index ee4bc039de6..f2d40d81d7b 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2058,9 +2058,9 @@ vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_ // support assembler for AMD64, we accept 64bit operand on vmovd so // that we can use one template for both SSE and AVX instructions. vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM } -vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Qword|BaseIndex, RegXMM } +vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, RegXMM } vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex } -vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Qword|BaseIndex } +vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|RegMem } vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM } vmovdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index a9f30fe2452..57eacbc0bd5 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -40876,8 +40876,8 @@ const insn_template i386_optab[] = 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, @@ -40913,8 +40913,8 @@ const insn_template i386_optab[] = { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, - { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "vmovd", 2, 0x666E, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,