From: lkcl <lkcl@web>
Date: Sat, 11 Sep 2021 11:51:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~163
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=290b9a970f1a8ce047bb692a7e837b1ea2e89723;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 5db0d7cbf..6cc6820b3 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -4,6 +4,7 @@ Links:
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
 * [[svp64]]
+* [[sv/branches]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element