From: Giacomo Travaglini Date: Wed, 18 Apr 2018 09:31:44 +0000 (+0100) Subject: arch-arm: Change disassemble when MSR to UNKNOWN register X-Git-Tag: v19.0.0.0~2146 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=291c2798103999b66f9ad5b9a885a67f3ef2160e;p=gem5.git arch-arm: Change disassemble when MSR to UNKNOWN register This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg --- diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 7752ba08f..00bd0770f 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -369,7 +369,14 @@ namespace Aarch64 } // Check for invalid registers if (miscReg == MISCREG_UNKNOWN) { - return new Unknown64(machInst); + auto full_mnemonic = + csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", + read ? "mrs" : "msr", + op0, op1, crn, crm, op2); + + return new FailUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic); + } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (miscReg == MISCREG_NZCV) { if (read)